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copyright ? cirrus logic, inc. 2006 (all rights reserved) advance product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. http://www.cirrus.com december '06 ds680a1 low power, stereo codec w/headphone & speaker amps stereo codec ? high performance stereo adc & dac ? 98 db dynamic range (a-wtd) ? -88 db thd+n ? flexible stereo analog input architecture ? 4:1 analog input mux ? analog input mixing ? analog passthru with volume control ? analog programmable gain amplifier (pga) ? programmable automatic level control (alc) ? noise gate for noise suppression ? programmable threshold & attack/release rates ? dual mic inputs ? differential or single-ended ? +16 db to +32 db w/1db step mic pre- amplifiers ? programmable, low noise mic bias levels ? digital signal processing engine ? bass & treble tone control, de-emphasis ? master vol. and independent pcm sdin + adc sdout mix volume control ? soft-ramp & zero-cross transitions ? programmable peak-detect and limiter ? beep generator w/full tone control class d stereo/mono speaker amplifier ? no external filter required ? high stereo output power at 10% thd+n ? 2 x 1.00 w into 8 @ 5.0 v ? 2 x 550 mw into 8 @ 3.7 v ? 2 x 230 mw into 8 @ 2.5 v ? high mono output power at 10% thd+n ? 1 x 1.90 w into 4 @ 5.0 v ? 1 x 1.00 w into 4 @ 3.7 v ? 1 x 350 mw into 4 @ 2.5 v ? direct battery powered operation ? battery level monitoring & compensation ? 82% efficiency at 800 mw ? phase-aligned pwm output reduces idle channel current ? spread spectrum modulation ? low quiescent current stereo headphone amplifier ? ground centered outputs ? no dc-blocking capacitors required ? integrated negativ e voltage regulator ? high power output at -75 db thd+n ? 2 x 23 mw into 16 @ 1.8 v ? 2 x 44 mw into 16 @ 2.5 v ( features continued on page 2 ) serial audio input/output i 2 c control +1.65 v to +3.47 v interface supply control port serial audio port level shifter multi-bit ? adc beep +1.65 v to +2.63 v analog supply multi-bit ? adc alc left hp/line output ground-centered amps mono mix, limiter, bass, treble adjust volume, mono swap, mix right hp/line output left inputs right inputs +1.65 v to +2.63 v headphone supply speaker/hp switch +1.60 v to +5.25 v battery charge pump +vhp -vhp +1.65 v to +2.63 v digital supply +1.65 v to +2.63 v analog supply pulse-width modulator (pwm) stereo/mono full-bridge speaker outputs temperature monitor battery level monitoring & compensation multi-bit ? dac mic bias hpf selectable bias voltage alc summing programmable gain amps +16 to +32 db diff./ s.e. mic pre-amps class d amps 1 2 3 4 1 2 3 4 + - + - reset CS42L52
2 ds680a1 CS42L52 system features ? 12, 24, and 27 mhz master clock support in addition to typical audio clock rates ? high performance 24-bit converters ? multi-bit delta sigma architecture ? very low 64fs oversampling clock reduces power consumption ? low power operation ? stereo analog passthru: 10 mw @ 1.8 v ? stereo playback: 14 mw @ 1.8 v ? stereo rec. and playback: 23 mw @ 1.8 v ? variable power supplies ? 1.8 v to 2.5 v digital & analog ? 1.6 v to 5 v class d amplifier ? 1.8 v to 2.5 v headphone amplifier ? 1.8 v to 3.3 v interface logic ? power down management ? adc, dac, codec, mic pre-amplifier, pga, headphone amplifier, speaker amplifier ? analog & digital routing/mixes: ? line/headphone out = analog in (adc bypassed) ? line/headphone/speaker out = adc + digital in ? digital out = adc + digital in ? internal digital loopback ? mono mixes ? flexible clocking options ? master or slave operation ? high impedance digital output option (for easy muxing between codec & other data sources) ? quarter-speed mode - (i.e. allows 8 khz fs while maintaining a flat noise floor up to 16 khz) ? 4 khz to 96 khz sample rates ? i2c ? control port operation ? temp. monitor w/thermal foldback & shutdown ? headphone/speaker detection input ? pop and click suppression applications ? digital voice recorders, digital cameras & camcorders ? pda?s ? personal media players ? portable game consoles general description the CS42L52 is a highly integr ated, low power stereo codec with headphone and class d speaker amplifiers. the CS42L52 offers many features suitable for low power, porta- ble system applications. the adc input path allows independent channel control of a number of features. input summ ing amplifiers mix and select line-level and/or microphone level inputs for each channel. the microphone input path includes a selectable programma- ble-gain pre-amplifier stage and a low noise mic bias voltage supply. a pga is available for line or microphone inputs and provides analog gain with soft ramp and zero cross transi- tions. the adc also features a digital volume control with soft ramp transitions. a programmable alc and noise gate mon- itor the input signals and adjust the volume levels appropriately. to conserve power, the adc may be bypassed while still allowing full analog volume control. the dac output path includes a digital signal processing en- gine with various fixed function controls.tone control provides bass and treble adjustment of four selectable corner frequen- cies. the digital mixer provides independent volume control for both the adc output and pcm input signal paths, as well as a master volume control. digital volume controls may be configured to change on soft ramp transitions while the analog controls can be configured to occur on every zero crossing. the dac also includes de-emphasis, limiting functions and a beep generator delivering tones selectable across a range of two full octaves. the stereo headphone amplifier is powered from a separate positive supply and the integrated charge pump provides a negative supply. this allows a ground-centered analog output with a wide signal swing and eliminates external dc-blocking capacitors. the class d stereo speaker amplifier does not require an external filter and provides the high efficiency amplification re- quired by power sensitive portable applications. the speaker amplifier may be powered directly from a battery while the in- ternal dc supply monitoring and compensation provides a constant gain level as the batt ery?s voltage deca ys. an internal temperature monitor alerts the user and automatically atten- uates and/or shuts down the pwm speaker output when an overload condition causes temperatures to exceed safe oper- ating levels. in addition to its many featur es, the CS42L52 operates from a low voltage analog and digital core making it ideal for portable systems that require extremely low power consumption in a minimal amount of space. the CS42L52 is available in a 40-pin qfn package in both commercial (-40 to +85 c) and automotive (-40 to +105 c) grades. the CS42L52 customer de monstration board is also available for device evaluation and implementation sugges- tions. please refer to ?ordering information? on page 82 for complete ordering information.
ds680a1 3 CS42L52 table of contents 1. pin descriptions ........................................................................................................... ................... 8 1.1 i/o pin characteristics ................................................................................................... ................... 9 2. typical connection diagram ................................................................................................. .. 10 3. characteristic and specificatio ns ............ ................. ................ ................ ................ ......... 11 recommended operating conditions ................................................................................... 11 absolute maximum ratings ...................................................................................................... .11 analog input characteristics (commercial - cnz) .......................................................... 12 analog input characteristics (automotive - dnz) .......................................................... 13 adc digital filter characteristics ....................................................................................... 14 analog output characteristics (commercial - cnz) ...................................................... 15 analog output characteristics (automotive - dnz) ...................................................... 16 analog passthru characteristics ................. ................ ................ ................ ............. ......... 17 pwm output characteristics (note 9) .................................................................................... 17 line output voltage level characteristics .. ................ ................ ............. ............. ......... 18 headphone output power characteristics ...................................................................... 19 combined dac interpolation & on-chip anal og filter response .. ................ ............ 20 switching specifications - serial port ............ ................ ................ ............. ............. ......... 21 switching specifications - i2c control port .. ................ ................ ............. ............. ......... 22 dc electrical characteristics .............................................................................................. 23 digital interface specifications & characteri stics ............ ................ ................ ......... 23 power consumption ............................................................................................................. ....... 24 4. applications ............................................................................................................... .................... 25 4.1 overview .................................................................................................................. ....................... 25 4.1.1 basic architecture ...................................................................................................... ........... 25 4.1.2 line & mic inputs ....................................................................................................... ........... 25 4.1.3 line & headphone outputs ................................................................................................ ... 25 4.1.4 speaker driver outputs ......................... ......................................................................... ....... 25 4.1.5 fixed function dsp engine ............................................................................................... ... 25 4.1.6 beep generator ........... ............................................................................................... ........... 25 4.1.7 power management ........................................................................................................ ...... 25 4.2 analog inputs ............................................................................................................ ..................... 26 4.2.1 mic inputs .............................................................................................................. ............... 27 4.2.2 automatic level control (alc) ........................................................................................... ... 27 4.2.3 noise gate .............................................................................................................. .............. 28 4.3 analog outputs ........................................................................................................... ................... 29 4.3.1 beep generator ........... ............................................................................................... ........... 30 4.3.2 limiter ................................................................................................................. ................... 31 4.4 analog in to analog out pa ssthru .......................................................................................... ........ 32 4.4.1 overriding the adc power down .......................................................................................... 3 2 4.4.2 overriding the pga power down .......................................................................................... 3 3 4.5 pwm outputs ............................................................................................................... .................. 33 4.5.1 mono speaker output config uration ..................................................................................... 33 4.5.2 vp battery compensation ................................................................................................. .... 33 4.5.2.1 maintaining a desired ou tput level ........................................................................... 34 4.6 serial port clocking ...................................................................................................... .................. 34 4.7 digital interface formats ... .............................................................................................. ............... 36 4.7.1 dsp mode ................................................................................................................ ............. 36 4.8 initialization ............................................................................................................ ......................... 36 4.9 recommended power-up sequence ............................................................................................. 37 4.10 recommended power- down sequence ...................................................................................... 37 4.11 control port operation ........................... ........................................................................ ............... 38 4.11.1 i2c control ............................................................................................................ ............... 38
4 ds680a1 CS42L52 4.11.2 memory addr ess pointer (map) .......................................................................................... 3 9 4.11.2.1 map increment (incr) ............................................................................................. 39 5. register quick reference ................................................................................................... ..... 40 6. register description ....................................................................................................... ........... 42 6.1 chip i.d. and revision register (address 01h) (read only) ......................................................... 42 6.1.1 chip i.d. (read only) ................................................................................................... ......... 42 6.1.2 chip revision (read only) ............................................................................................... ..... 42 6.2 power control 1 (address 02h) ................... .......................................................................... ......... 42 6.2.1 power down adc charge pump .......................................................................................... 42 6.2.2 power down pgax ......................................................................................................... ....... 42 6.2.3 power down adcx ......................................................................................................... ....... 43 6.2.4 power down .............................................................................................................. ............ 43 6.3 power control 2 (address 03h) ................... .......................................................................... ......... 43 6.3.1 power down adc override ................................................................................................. .. 43 6.3.2 power down micx ......................................................................................................... ........ 43 6.3.3 power down mic bias ..................................................................................................... ..... 43 6.4 power control 3 (address 04h) ................... .......................................................................... ......... 44 6.4.1 headphone power control ................................................................................................. ... 44 6.4.2 speaker power control ................................................................................................... ...... 44 6.5 clocking control (address 05h) ............................................................................................ .......... 44 6.5.1 auto-detect ............................................................................................................. .............. 44 6.5.2 speed mode .............................................................................................................. ............ 45 6.5.3 32khz sample rate group ................................................................................................. .. 45 6.5.4 27 mhz video clock ...................................................................................................... ........ 45 6.5.5 internal mclk/lrck ratio ................................................................................................ ... 45 6.5.6 mclk divide by 2 ........................................................................................................ ......... 46 6.6 interface control 1 (address 06h) ......................................................................................... ......... 46 6.6.1 master/slave mode .................................. ..................................................................... ........ 46 6.6.2 sclk polarity ........................................................................................................... ............. 46 6.6.3 adc interface format .................................................................................................... ....... 46 6.6.4 dsp mode ................................................................................................................ ............. 46 6.6.5 dac interface format .................................................................................................... ....... 47 6.6.6 audio word length ....................................................................................................... ......... 47 6.7 interface control 2 (address 07h) ......................................................................................... ......... 47 6.7.1 sclk equals mclk ........................................................................................................ ...... 47 6.7.2 sdout to sdin digital loopback ......................................................................................... 4 7 6.7.3 tri-state serial port interface ......................................................................................... ....... 48 6.7.4 speaker/headphone switch invert ........................................................................................ 4 8 6.7.5 mic bias level .......................................................................................................... ............ 48 6.8 input x select: adca and pgaa (address 08h), adcb and pgab (address 09h) ....................... 48 6.8.1 adc input select ................................... ..................................................................... ........... 48 6.8.2 pga input mapping ....................................................................................................... ........ 49 6.9 analog & hpf control (address 0ah) ........................................................................................ .... 49 6.9.1 adcx high-pass filter ... ................................................................................................ ....... 49 6.9.2 adcx high-pass filter free ze ............................................................................................ .. 49 6.9.3 ch. x analog soft ramp .................................................................................................. ...... 49 6.9.4 ch. x analog zero cross ................................................................................................. ...... 49 6.10 adc hpf corner frequency (a ddress 0bh) ................................................................................ 50 6.10.1 hpf x corner frequency ................................................................................................. ... 50 6.11 misc. adc control (address 0ch) .......................................................................................... ...... 50 6.11.1 adc channel b=a ........................................................................................................ ...... 50 6.11.2 digital mux ............................................................................................................ ............. 50 6.11.3 digital sum ............................................................................................................ .............. 50 6.11.4 invert adc signal polarity ................ ............................................................................. ...... 50
ds680a1 5 CS42L52 6.11.5 adc mute ............................................................................................................... ............. 51 6.12 playback control 1 (address 0dh) ......................................................................................... ...... 51 6.12.1 headphone analog gain .................................................................................................. ... 51 6.12.2 playback volume setting b=a .................. .......................................................................... 51 6.12.3 invert pcm signal polarity .................. ........................................................................... ..... 51 6.12.4 master playback mute ................................................................................................... ...... 51 6.13 miscellaneous controls (address 0eh) ..................................................................................... ... 52 6.13.1 passthru analog ........................................................................................................ .......... 52 6.13.2 passthru mute .......................................................................................................... ........... 52 6.13.3 freeze registers ....................................................................................................... .......... 52 6.13.4 hp/speaker de-emphasis ................................................................................................. .52 6.13.5 digital soft ramp ...................................................................................................... .......... 53 6.13.6 digital zero cross ..................................................................................................... ........... 53 6.14 playback control 2 (address 0fh) ................ ......................................................................... ....... 53 6.14.1 headphone mute ......................................................................................................... ........ 53 6.14.2 speaker mute ........................................................................................................... ........... 53 6.14.3 speaker volume setting b=a ............................................................................................. .54 6.14.4 speaker channel swap ................................................................................................... .... 54 6.14.5 speaker mono control ................................................................................................... ... 54 6.14.6 speaker mute 50/50 control ............................................................................................. .. 54 6.15 micx amp control: mic a (address 10h) & mic b (address 11h) ..................................................................................... .54 6.15.1 mic x select ........................................................................................................... ............. 54 6.15.2 micx configuration ..................................................................................................... ......... 55 6.15.3 micx gain .............................................................................................................. ............. 55 6.16 pgax vol. & alcx transition ctl.: alc, pga a (address 12h) & alc, pga b (address 13h) .................................................................. 55 6.16.1 alcx soft ramp disable ................................................................................................. .... 55 6.16.2 alcx zero cross disable ....................... ......................................................................... .... 55 6.16.3 pgax volume ............................................................................................................ .......... 56 6.17 passthru x volume: passavol (address 14h) & passbvol (address 15h) ....... ............. ...... 56 6.17.1 passthru x volume ...................................................................................................... ........ 56 6.18 adcx volume control: adc avol (address 16h) & adcbvol (add ress 17h) .......................... 57 6.18.1 adcx volume ............................................................................................................ .......... 57 6.19 adcx mixer volume: adca (address 18h) & adcb (address 19h ) ............................................ 58 6.19.1 adc mixer channel x mute ............................................................................................... .. 58 6.19.2 adc mixer channel x volume ............................................................................................. 58 6.20 pcmx mixer volume: pcma (address 1ah) & pc mb (address 1bh) .......................................... 58 6.20.1 pcm mixer channel x mute ............................................................................................... .58 6.20.2 pcm mixer channel x volume ............................................................................................ 5 8 6.21 beep frequency & on time (address 1ch) ................................................................................. 59 6.21.1 beep frequency ......................................................................................................... ......... 59 6.21.2 beep on time ........................................................................................................... .......... 60 6.22 beep volume & off time (address 1dh) ..................................................................................... .60 6.22.1 beep off time .......................................................................................................... ........... 60 6.22.2 beep volume ............................................................................................................ ........... 61 6.23 beep & tone configuration (address 1eh) .. ................................................................................ 61 6.23.1 beep configuration ..................................................................................................... ......... 61 6.23.2 beep mix disable ....................................................................................................... ......... 61 6.23.3 treble corner frequency ................................................................................................ .... 62 6.23.4 bass corner frequency .................................................................................................. .... 62 6.23.5 tone control enable .................................................................................................... ....... 62 6.24 tone control (address 1fh) ............................................................................................... .......... 62 6.24.1 treble gain ............................................................................................................ .............. 62
6 ds680a1 CS42L52 6.24.2 bass gain ............... ............................................................................................... .............. 63 6.25 master volume control: msta (address 20h) & mstb (address 21h) ....................................... 63 6.25.1 master volume control .................................................................................................. ...... 63 6.26 headphone volume control: hpa (address 2 2h) & hpb (address 23h) ..................................... 63 6.26.1 headphone volume contro l ............................................................................................... .63 6.27 speaker volume co ntrol: spka (address 24h) & spkb (add ress 25h) ................ ............. ......... 64 6.27.1 speaker volume control ................................................................................................. .... 64 6.28 adc & pcm channel mixer (address 26h) .................................................................................. 64 6.28.1 pcm mix channel swap ................................................................................................... .. 64 6.28.2 adc mix channel swap ................................................................................................... ... 64 6.29 limiter control 1, min/max thresholds (addre ss 27h) ................................................................. 65 6.29.1 limiter maximum threshol d .............................................................................................. .. 65 6.29.2 limiter cushion threshol d .............................................................................................. .... 65 6.29.3 limiter soft ramp disab le .............................................................................................. ..... 65 6.29.4 limiter zero cross disa ble ............................................................................................. ..... 66 6.30 limiter control 2, release rate (address 2 8h) ............................................................................ 66 6.30.1 peak detect and limiter ...................... .......................................................................... ...... 66 6.30.2 peak signal limit all channels ......................................................................................... .. 66 6.30.3 limiter release rate . .................................................................................................. ........ 66 6.31 limiter attack rate (address 29h) ........................................................................................ ........ 67 6.31.1 limiter attack rate ........................... ......................................................................... .......... 67 6.32 alc enable & attack rate (address 2ah) ................................................................................... 67 6.32.1 alcx enable ............. ............................................................................................... ........... 67 6.32.2 alc attack rate ........................................................................................................ .......... 67 6.33 alc release rate (address 2bh) ........................................................................................... ..... 68 6.33.1 alc release rate ............................... ........................................................................ ........ 68 6.34 alc threshold (address 2ch) .................. ............................................................................ ....... 68 6.34.1 alc maximum threshold . ................................................................................................. .. 68 6.34.2 alc minimum threshold .. ................................................................................................ ... 69 6.35 noise gate control (addre ss 2dh) ......................................................................................... ...... 69 6.35.1 noise gate all channels ................................................................................................ ..... 69 6.35.2 noise gate enable ...................................................................................................... ........ 69 6.35.3 noise gate threshold and boost ........................................................................................ 7 0 6.35.4 noise gate delay timing ................................................................................................ .... 70 6.36 status (address 2eh) (read only) ......................................................................................... ...... 70 6.36.1 serial port clock error (read only) .................................................................................... 70 6.36.2 dsp engine overflow (read only) ........... .......................................................................... 71 6.36.3 pcmx overflow (read only) .............................................................................................. .71 6.36.4 adcx overflow (read only) .............................................................................................. .71 6.37 battery compensation (address 2fh) .......... ............................................................................. ... 71 6.37.1 battery compensa tion ................................................................................................... ...... 71 6.37.2 vp monitor ............................................................................................................. .............. 71 6.37.3 vp reference .. ......................................................................................................... ........... 72 6.38 vp battery level (address 30h) (read only) ............................................................................... 72 6.38.1 vp voltage level (read only) ........................................................................................... .72 6.39 speaker status (address 31 h) (read only) ................................................................................. 72 6.39.1 speaker current lo ad status (read only) ......................................................................... 72 6.39.2 spkr/hp pin status (read only) ....................................................................................... 73 6.39.3 thermal warning status (read only) ................................................................................. 73 6.39.4 thermal error status (read only) ....................................................................................... 73 6.40 temperature monitor control (address 32h) ................................................................................ 73 6.40.1 temperature acknowledge & release ................................................................................ 73 6.40.2 thermal foldback (address 33h) .............. .......................................................................... 7 3 6.40.3 thermal foldback ................................ ....................................................................... ......... 73
ds680a1 7 CS42L52 6.40.4 speaker attenuation .................................................................................................... ........ 74 6.41 charge pump frequency (addr ess 34h) ...................................................................................... 74 6.41.1 charge pump frequency .......................... ........................................................................ .. 74 7. analog performance plots ................................................................................................... .75 7.1 headphone thd+n versus output power plots .. .......................................................................... 75 8. example system clock frequenc ies .......... ................. ................ ................ ................ ......... 77 8.1 auto detect enabled .......................... .......................................................................... ................ 77 8.2 auto detect disabled .................................................................................................... ................ 77 9. pcb layout considerations .................................................................................................. ... 78 9.1 power supply, grounding ................................................................................................... ............ 78 9.2 qfn thermal pad ........................................................................................................... ............... 78 10. adc & dac digital filters ................................................................................................ ........ 79 11. parameter definitions ..................................................................................................... ......... 80 12. package dimensions ........................................................................................................ .......... 81 thermal characteristics ....................................................................................................... .81 13. ordering information ...................................................................................................... ........ 82 14. references ................................................................................................................ .................... 82 15. revision history .......................................................................................................... ................ 82 list of figures figure 1. typical connection diagram .......................................................................................... ............ 10 figure 2. headphone output test load .......................................................................................... .......... 19 figure 3. serial audio interface timing ........... ............................................................................ .............. 21 figure 4. control port timing - i2c ........................................................................................... ................. 22 figure 5. analog input signal flow ............................................................................................ ............... 26 figure 6. single-ended mic configuration ............ .......................................................................... ......... 27 figure 7. differential mic configuration ...................................................................................... .............. 27 figure 8. alc ................................................................................................................. ........................... 28 figure 9. noise gate attenuation .............................................................................................. ................ 28 figure 10. dsp engine signal flow ............................................................................................. ............. 29 figure 11. pwm output stage ................................................................................................... ............... 30 figure 12. analog output stage ................................................................................................ ................ 30 figure 13. beep configuration options .............. ........................................................................... ............ 31 figure 14. peak detect & limiter .............................................................................................. ................ 32 figure 15. battery compensation ............................................................................................... .............. 34 figure 16. i2s format ......................................................................................................... ....................... 36 figure 17. left-justified format .............................................................................................. .................. 36 figure 18. right-justified format (dac only) .................................................................................. ......... 36 figure 19. dsp mode format) ................................................................................................... ............... 36 figure 20. control port timing, i2c write ..................................................................................... ............. 38 figure 21. control port timing, i2c read ........ .............................................................................. ............ 38 figure 22. thd+n vs. output power per channel at 1.8 v (16 load) ................................................... 75 figure 23. thd+n vs. output power per channel at 2.5 v (16 load) ................................................... 75 figure 24. thd+n vs. output power per channel at 1.8 v (32 load) ................................................... 76 figure 25. thd+n vs. output power per channel at 2.5 v (32 load) ................................................... 76 figure 26. adc passband ripple ................................................................................................ ............. 79 figure 27. adc stopband rejection ............................................................................................. ............ 79 figure 28. adc transition band ................................................................................................ ............... 79 figure 29. adc transition band detail ......................................................................................... ............ 79 figure 30. dac passband ripple ................................................................................................ ............. 79 figure 31. dac stopband ....................................................................................................... .................. 79 figure 32. dac transition band ................................................................................................ ............... 79 figure 33. dac transition band (detail) ....................................................................................... ............ 79
8 ds680a1 CS42L52 1. pin descriptions pin name # pin description sda 1 serial control data ( input / output ) - sda is a data i/o in i2c mode. scl 2 serial control port clock ( input ) - serial clock for the serial control port. tstn 3 test in - this pin is an input used for test purposes only. it must be tied to ground for normal oper- ation. spkr_outa+ spkr_outa- spkr_outb+ spkr_outb- 4 6 7 9 pwm speaker output ( output ) - full-bridge amplified pwm speaker outputs. vp 5 8 power for pwm drivers ( input ) - power supply for the pwm output driver stages. -vhpfilt 10 inverting charge pump filter connection (output) - power supply from the inverting charge pump that provides the negative rail for the headphone/line amplifiers. flyn 11 charge pump cap negative node (output) - negative node for the inverting charge pump?s fly- ing capacitor. flyp 12 charge pump cap positive node (output) - positive node for the inverting charge pump?s flying capacitor. +vhp 13 positive analog power for headphone ( input ) - positive voltage rail and power for the internal headphone amplifiers and inverting charge pump. hp/line_outb, a 14,15 headphone/line audio output ( output ) - stereo headphone or line level analog outputs. 12 11 13 14 15 16 17 18 19 20 29 30 28 27 26 25 24 23 22 21 39 40 38 37 36 35 34 33 32 31 2 1 3 4 5 6 7 8 9 10 gnd/thermal pad sdout mclk sclk sdin sda lrck flyn +vhp hp/line_outb hp/line_outa vq micbias ain4a/mic1+/mic2a ain2a tstn spkr_outa+ vp vp vd spkr_outb- -vhpfilt ain4b/mic2+/mic2b ain1b ain2b afiltb ain3b/mic2-/mic1b afilta ain1a ain3a/mic1-/mic1a spkr_outb+ scl dgnd spkr_outa- flyp va agnd filt+ reset vl spkr/hp top-down (through-package) view 40-pin qfn package
ds680a1 9 CS42L52 1.1 i/o pin characteristics input and output levels and associ ated power supply voltage are shown in the table below. logic levels should not exceed the corresponding power supply voltage. va 16 analog power ( input ) - positive power for the internal analog section. agnd 17 analog ground ( input ) - ground reference for the internal analog section. filt+ 18 positive voltage reference ( output ) - positive reference voltage for the internal sampling cir- cuits. vq 19 quiescent voltage ( output ) - filter connection for the internal quiescent voltage. micbias 20 microphone bias ( output ) - low noise bias supply for an external microphone. electrical charac- teristics are specified in the dc electrical characteristics table. ain4a,b ain3a,b 21,22 23,24 line-level analog inputs ( input ) - single-ended stereo line-level analog inputs. mic1+,- mic2+,- 21,23 22,24 differential microphone inputs ( input ) - differential stereo microphone inputs. mic2a,b mic1a,b 21,22 23,24 single-ended microphone inputs ( input ) - single-ended stereo microphone inputs. ain2a,b ain1a,b 25,26 29,30 line-level analog inputs ( input ) - single-ended stereo line-level analog inputs. afilta,b 27,28 anti-alias filter connection ( output ) - anti-alias filter connection for the adc inputs. spkr/hp 31 speaker/headphone switch ( input ) - powers down the left and/or right channel of the speaker and/or headphone outputs. reset 32 reset ( input ) - the device enters a low power mode when this pin is driven low. vl 33 digital interface power ( input ) - determines the required signal level for the serial audio inter- face and host control port. vd 34 digital power ( input ) - positive power for the internal digital section. dgnd 35 digital ground ( input ) - ground reference for the internal digital section. sdout 36 serial audio data output ( output ) - output for two?s complement serial audio data. mclk 37 master clock ( input ) - clock source for the delta-sigma modulators. sclk 38 serial clock ( input/output ) - serial clock for the serial audio interface. sdin 39 serial audio data input ( input ) - input for two?s complement serial audio data. lrck 40 left right clock ( input/output ) - determines which channel, left or right, is currently active on the serial audio data line. gnd/thermal pad - ground reference for pwm power fets and charge pump; thermal relief pad for optimized heat dissipation. power supply pin name i/o driver receiver vl reset input - 1.65 v - 3.47 v, with hysteresis scl input - 1.65 v - 3.47 v, with hysteresis sda input/output 1.65 v - 3.47 v, cmos/open drain 1.65 v - 3.47 v, with hysteresis mclk input - 1.65 v - 3.47 v lrck input/output 1.65 v - 3. 47 v, cmos 1.65 v - 3.47 v sclk input/output 1.65 v - 3. 47 v, cmos 1.65 v - 3.47 v sdout output 1.65 v - 3.47 v v, cmos sdin input - 1.65 v - 3.47 v va spkr/hp input - 1.65 v - 2.63 v vp spkr_outa+ output 1.6 v - 5.25 v power mosfet - spkr_outa- output 1.6 v - 5.25 v power mosfet - spkr_outb+ output 1.6 v - 5.25 v power mosfet - spkr_outb- output 1.6 v - 5.25 v power mosfet -
10 ds680a1 CS42L52 2. typical connection diagram note 4 note 3 note 2 note 1 1 f +1.8 v to +2.5 v 0.1 f 1 f dgnd vl 0.1 f +1.8 v to +3.3 v scl sda reset 2 k lrck digital audio processor mclk sclk vd mic1- ain3a/mic1a microphone 1 sdin sdout CS42L52 2 k micbias +1.8 v to +2.5 v hp/line_outb hp/line_outa ain1a left 1 1800 pf 1800 pf 100 k 100 ain1b right 1 * * r l 0.1 f va headphone out left & right line level out left & right flyp flyn -vhpfilt 0.1 f 51.1 0.022 f 100 k 100 spkr_outa+ spkr_outa- spkr/hp 51.1 0.022 f mic1+ ain4a/mic2a mic2+ ain4b/mic2b microphone 2 mic2- ain3b/mic1b 100 k r l 100 k 1 f 1 f 0.1 f +vhp 1 f 10 f vq agnd * capacitors must be c0g or equivalent 150 pf afilta afiltb 150 pf 1 f ** filt+ 1 f 1 f 1 f 1 f * *use low esr ceramic capacitors. ** ** see note 5 spkr_outb+ spkr_outb- 1 f vp vp +1.6 v to +5 v stereo speakers ain2a left 2 1800 pf 1800 pf 100 k 100 ain2b right 2 * * 100 k 100 1 f 1 f 0.1 f 0.1 f analog input 1 analog input 2 10 f mic-level inputs 47 k notes: 1. recommended values for the default charge pump switching frequency. the required capacitance follows an inverse relationship with the charge pump?s switching frequency. when increasing the switching frequency, the capacitance may decrease; when lowering the switching frequency, the capacitance must increase. 2. larger capacitance reduces the ripple on the internal amplifier?s supply. this may reduce the distortion at higher output power levels. 3. additional bulk capacitance may be added to improve psrr at low frequencies. 4. these capacitors serve as a charge reservoir for the internal switched capacitor adc modulators. they are only needed when the pga (programmable gain amplifier) is bypassed. 5. series resistance in the path of the power supplies must be avoided. any voltage drop on vhp will directly impact the negative charge pump supply (-vhpfilt) and clip the audio output. 6. the value of r l , a current-limiting resistor used with electret condenser microphones, is dictated by the microphone cartridge. 7. the negative terminal of the micx inputs connects to the ground pin of the microphone cartridge. gain is applied only to the positive terminal. note 6 note 7 note 7 figure 1. typical connection diagram
ds680a1 11 CS42L52 3. characteristic a nd specifications recommended operating conditions (agnd=dgnd=0 v, all voltages with respect to ground.) absolute maximum ratings (agnd = dgnd = 0 v; all voltages with respect to ground.) warning: operation at or beyond these limit s may result in permanent damage to the device. normal operation is not guaranteed at these extremes. notes: 1. any pin except supplies. transien t currents of up to 100 ma on the analog input pins will not cause scr latch-up. 2. the maximum over/under voltage is limited by the input current. parameters symbol min max units dc power supply analog va 1.65 2.63 v headphone amplifier +vhp 1.65 2.63 v speaker amplifier vp 1.60 5.25 v digital vd 1.65 2.63 v serial/control port interface vl 1.65 3.47 v ambient temperature commercial - cnz automotive - dnz t a -40 -40 +85 +105 c c parameters symbol min max units dc power supply analog speaker digital serial/control port interface va, vhp vp vd vl -0.3 -0.3 -0.3 -0.3 3.0 5.5 3.0 4.0 v v v v input current (note 1) i in -10ma analog input voltage (note 2) v in agnd-0.7 va+0.7 v digital input voltage (note 2) v ind -0.3 vl+ 0.4 v ambient operating temper ature (power applied) t a -50 +115 c storage temperature t stg -65 +150 c
12 ds680a1 CS42L52 analog input ch aracteristics (c ommercial - cnz) (test conditions (unless otherwise specified): input sine wave (re lative to digital full-scale): 1 khz through passive input fil ter; vl = vd = vhp = 1.8 v; t a = +25 c; measurement bandwidth is 10 hz to 20 kh z unless otherwise specified. sample fre- quency = 48 khz) 3. measured with dac delivering full-scale output into specified load. 4. measured between analog input and agnd. va = 2.5v va = 1.8v parameters min typ max min typ max unit analog in to adc (pga bypassed) dynamic range a-weighted unweighted 93 90 99 96 - - 90 87 96 93 - - db db total harmonic distortion + noise -1 dbfs -20 dbfs -60 dbfs - - - -86 -76 -36 -80 - -30 - - - -84 -73 -33 -78 - -27 db db db analog in to pga to adc dynamic range pga setting: 0 db a-weighted unweighted 92 89 98 95 - - 89 86 95 92 - - db db pga setting: + 12 db a-weighted unweighted 85 82 91 88 - - 82 79 88 85 - - db db total harmonic distortion + noise pga setting: 0 db -1 dbfs -60 dbfs - - -88 -35 -82 -29 - - -86 -32 -80 -26 db db pga setting: +12 db -1 dbfs - -85 -79 - -83 -77 db analog in to mic pre-amp (+16 db) to pga to adc dynamic range pga setting: 0 db a-weighted unweighted - - 86 83 - - - - 83 80 - - db db total harmonic distortion + noise pga setting: 0 db -1 dbfs - -76 - - -74 - db analog in to mic pre-amp (+32 db) to pga to adc dynamic range pga setting: 0 db a-weighted unweighted - - 78 74 - - - - 75 71 - - db db total harmonic distortion + noise pga setting: 0 db -2 dbfs - -74 - - -71 - db other characteristics dc accuracy interchannel gain mismatch - 0.2 - - 0.2 - db gain drift - 100 - - 100 - ppm/c offset error sdout code with hpf on - 352 - - 352 - lsb input interchannel isolation - 90 - - 90 - db hp amp to analog input isolation r l = 10 k (note 3) r l = 16 - - 100 70 - - - - 100 70 - - db db speaker amp to analog input isolation - 60 - - 60 - db full-scale input voltage adc pga (0 db) pga (+12 db) mic (+16 db) mic (+32 db) 0.73?va 0.73?va 0.769?va 0.770?va 0.194?va 0.115?va 0.019?va 0.83?va 0.83?va 0.73?va 0.73?va 0.769?va 0.770?va 0.194?va 0.115?va 0.019?va 0.83?va 0.83?va vpp vpp vpp vpp input impedance (note 4) adc pga mic - - - 20 39 50 - - - - - - 20 39 50 - - - k k k
ds680a1 13 CS42L52 analog input characterist ics (automotive - dnz) (test conditions (unless otherwise specified): input sine wave (relative to full-scale): 1 khz through passive input filter; vl = vd = vhp = 1.8 v; t a = -40 to +85 c; measurement bandwidth is 10 hz to 20 khz unless otherwise specified. sample frequency = 48 khz) va = 2.37 - 2.63 v va = 1.65 - 1.89 v parameters min typ max min typ max unit analog in to adc dynamic range a-weighted unweighted 91 88 99 96 - - 88 85 96 93 - - db db total harmonic distortion + noise -1 dbfs -20 dbfs -60 dbfs - - - -86 -76 -36 -78 - -28 - - - -84 -73 -33 -76 - -25 db db db analog in to pga to adc dynamic range pga setting: 0 db a-weighted unweighted 90 87 98 95 - - 87 84 95 92 - - db db pga setting: +12 db a-weighted unweighted 83 80 91 88 - - 80 77 88 85 - - db db total harmonic distortion + noise pga setting: 0 db -1 dbfs -60 dbfs - - -88 -35 -80 -27 - - -86 -32 -78 -24 db db pga setting: +12 db -1 dbfs - -85 -77 - -83 -75 db analog in to mi c pre-amp (+16 db) to pga to adc dynamic range pga setting: 0 db a-weighted unweighted - - 86 83 - - - - 83 80 - - db db total harmonic distortion + noise pga setting: 0 db -1 dbfs - -76 - - -74 - db analog in to mi c pre-amp (+32 db) to pga to adc dynamic range pga setting: 0 db a-weighted unweighted - - 78 74 - - - - 75 71 - - db db total harmonic distortion + noise pga setting: 0 db -2 dbfs - -74 - - -71 - db other characteristics dc accuracy interchannel gain mismatch - 0.1 - - 0.1 - db gain drift - 100 - - 100 - ppm/c offset error sdout code with hpf on - 352 - - 352 - lsb input interchannel isolation - 90 - - 90 - db hp amp to analog input isolation r l = 10 k (note 3) r l = 16 - - 100 70 - - - - 100 70 - - db db speaker amp to analog input isolation - 60 - - 60 - db full-scale input voltage adc pga (0 db) pga (+12 db) mic (+16 db) mic (+32 db) 0.73?va 0.73?va 0.769?va 0.770?va 0.194?va 0.115?va 0.019?va 0.83?va 0.83?va 0.73?va 0.73?va 0.769?va 0.770?va 0.194?va 0.115?va 0.019?va 0.83?va 0.83?va vpp vpp vpp vpp input impedance (note 4) adc pga mic 18 40 50 - - - - - - 18 40 50 - - - - - - k k k
14 ds680a1 CS42L52 adc digital filter characteristics 5. response is clock-dependent and will scale with fs. note that the response plots ( figures 26 to 29 on page 79 ) have been normalized to fs and can be de-normali zed by multiplying the x-axis scale by fs. hpf parameters are for fs = 48 khz. parameters (note 5) min typ max unit passband (frequency response) to -0.1 db corner 0 - 0.4948 fs passband ripple -0.09 - 0.17 db stopband 0.6 - - fs stopband attenuation 33 - - db total group delay -7.6/fs- s high-pass filter characteristics (48 khz fs) frequency response -3.0 db -0.13 db - - 3.6 24.2 - - hz hz phase deviation @ 20 hz - 10 - deg passband ripple - - 0.17 db filter settling time -10 5 /fs 0 s
ds680a1 15 CS42L52 analog output characteris tics (commercial - cnz) (test conditions (unless otherwise specifie d): input test signal is a full-scale 997 hz sine wave; vl = vd = vhp = 1.8 v; t a = +25 c; measurement bandwidth is 10 hz to 20 kh z; sample frequency = 48 khz; test load r l = 10 k , c l = 10 pf for the line output (see figure 2 ), and test load r l = 16 , c l = 10 pf (see figure 2 ) for the headphone output. hp_gain[2:0] = 011.) 6. one-half lsb of triangular pdf dither is added to data. 7. full-scale output voltage and power is determ ined by the gain setting, g, in register ?headphone analog gain? on page 51 . high gain settings at certain va and vhp su pply levels may cause clipping when the audio signal approaches full-scale, maximum power output, as shown in figures 22 - 25 on page 76 . va = 2.5 v va = 1.8 v parameters (note 6) min typ max min typ max unit r l = 10 k dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 92 89 - - 98 95 96 93 - - - - 89 86 - - 95 92 93 90 - - - - db db db db total harmonic distortion + noise 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -86 -75 -35 -86 -73 -33 -80 - -29 - - - - - - - - - -88 -72 -32 -88 -70 -30 -82 - -26 - - - db db db db db db r l = 16 dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 92 89 - - 98 95 96 93 - - - - 89 86 - - 95 92 93 90 - - - - db db db db total harmonic distortion + noise 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -75 -75 -35 -75 -73 -33 -69 - -29 - - - - - - - - - -75 -72 -32 -75 -70 -30 -69 - -26 - - - db db db db db db other characteristics for r l = 16 or 10 k output parameters modulation index (mi) (note 7) analog gain multiplier (g) - 0.6787 0.6047 - - 0.6787 0.6047 - full-scale output voltage (2?g?mi?va) (note 7) refer to table ?line output voltage level characteris- tics? on page 18 vpp full-scale output power (note 7) refer to table ?headphone output power characteristics? on page 19 interchannel isolation (1 khz) 16 10 k - - 80 95 - - - - 80 93 - - db db speaker amp to hp amp isolation - 80 - - 80 - db interchannel gain mismatch - 0.1 0.25 - 0.1 0.25 db gain drift - 100 - - 100 - ppm/c ac-load resistance (r l ) (note 8) 16 - - 16 - - load capacitance (c l ) (note 8) - - 150 - - 150 pf
16 ds680a1 CS42L52 analog output characteris tics (automotive - dnz) (test conditions (unless otherwise specified): input test signal is a full-scale 997 hz sine wave; vl = vd = vhp = 1.8 v; t a = -40 to +85 c; measurement bandwidth is 10 hz to 20 khz; sample frequency = 48 khz and 96 khz; test load r l = 10 k , c l = 10 pf for the line output (see figure 2 ), and test load r l = 16 , c l = 10 pf (see figure 2 ) for the headphone output. hpgain[2:0] = 011.) 8. see figure 2 . r l and c l reflect the recommended minimum resi stance and maximum capacitance re- quired for the internal op-amp's stability and signal integrity. in this circuit topology, c l will effectively move the band-limiting pole of the amp in the outp ut stage. increasing this value beyond the recom- mended 150 pf can cause the internal op-amp to become unstable. va = 2.37 - 2.5 v va = 1.65 - 1.89 v parameters (note 6) min typ max min typ max unit r l = 10 k dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 90 87 - - 98 95 96 93 - - - - 87 84 - - 95 92 93 90 - - - - db db db db total harmonic distortion + noise 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -86 -75 -35 -86 -73 -33 -78 - -27 - - - - - - - - - -88 -72 -32 -88 -70 -30 -80 - -24 - - - db db db db db db r l = 16 dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 90 87 - - 98 95 96 93 - - - - 87 84 - - 95 92 93 90 - - - - db db db db total harmonic distortion + noise 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db - - - - - - -75 -75 -35 -75 -73 -33 -67 - -27 - - - - - - - - - -75 -72 -32 -75 -70 -30 -67 - -24 - - - db db db db db db other characteristics for r l = 16 or 10 k output parameters mo dulation index (mi) (note 7) analog gain multiplier (g) - 0.6787 0.6047 - - 0.6787 0.6047 - full-scale output voltage (2?g?mi?va) (note 7) refer to the table in ?line output voltage level charac- teristics? on page 18 vpp full-scale output power (note 7) refer to the table in ?headphone output power characteristics? on page 19 interchannel isolation (1 khz) 16 10 k - - 80 95 - - - - 80 93 - - db db speaker amp to hp amp isolation - 80 - - 80 - db interchannel gain mismatch - 0.1 0.25 - 0.1 0.25 db gain drift - 100 - - 100 - ppm/c ac-load resistance (r l ) (note 8) 16 - - 16 - - load capacitance (c l ) (note 8) - - 150 - - 150 pf
ds680a1 17 CS42L52 analog passthru characteristics (test conditions (unless otherwise specified): input sine wave (relative to full-scale): 1 khz through passive input filter; vl = vd = vhp = 1.8 v; t a = +25 c; measurement bandwidth is 10 hz to 20 kh z unless otherwise specified. sample fre- quency = 48 khz) pwm output characteristics (note 9) (test conditions (unless otherwise specified): input test signal is a full scale 997 hz signal; measurement bandwidth is 10 hz t o 20 khz; mclk = 12.2880 mhz, sample frequency = 48 khz; test load r l = 8 for stereo full-bridge, r l = 4 for mono parallel full-bridge; vd = vl = va = vhp = 1.8v; pwm modulation index of 0.85, pwm switch rate = 384 khz) va = 2.5 v va = 1.8 v parameters min typ max min typ max unit analog in to hp/line amp dynamic range a-weighted unweighted - - 96 93 - - - - 94 91 - - db db total harmonic distortion + noise -1 dbfs -20 dbfs -60 dbfs - - - -80 -73 -33 - - - - - - -80 -71 -31 - - - db db db passband ripple 0/-0.3 0/-0.3 db parameters (note 10) symbol conditions min typ max units vp = 5.0 v power output per channel p o stereo full-bridge thd+n < 10% thd+n < 1% - - 1.00 0.80 - - w rms w rms mono parallel full-bridge thd+n < 10% thd+n < 1% - - 1.90 1.50 - - w rms w rms total harmonic distortion + noise thd+n stereo full-bridge p o = 0 dbfs = 0.8w - 0.52 - % mono parallel full-bridge p o = -3 dbfs = 0.75 w p o = 0 dbfs = 1.5 w - - 0.10 0.50 - - % % dynamic range dr stereo full-bridge p o = -60 dbfs, a-weighted p o = -60 dbfs, unweighted - - 91 88 - - db db mono parallel full-bridge p o = -60 dbfs, a-weighted p o = -60 dbfs, unweighted - - 91 88 - - db db vp = 3.7 v power output per channel p o stereo full-bridge thd+n < 10% thd+n < 1% - - 0.55 0.45 - - w rms w rms mono parallel full-bridge thd+n < 10% thd+n < 1% - - 1.00 0.84 - - w rms w rms total harmonic distortion + noise thd+n stereo full-bridge p o = 0 dbfs = 0.43 w - 0.54 - % mono parallel full-bridge p o = -3 dbfs = 0.41 w p o = 0 dbfs = 0.81 w - - 0.09 0.45 - - % % dynamic range dr stereo full-bridge p o = -60 dbfs, a-weighted p o = -60 dbfs, unweighted - - 91 88 - - db db mono parallel full-bridge p o = -60 dbfs, a-weighted p o = -60 dbfs, unweighted - - 95 92 - - db db
18 ds680a1 CS42L52 9. the pwm driver should be used in captive speaker systems only. 10. optimal pwm performance is achieved when mclk > 12 mhz. line output voltage level characteristics test conditions (unless otherwise specified): input test signal is a full-scale 997 hz sine wave; measurement bandwidth is 10 hz to 20 khz; sample frequency = 48 khz; test load r l = 10 k , c l = 10 pf (see figure 2 ). vp =2.5 v power output per channel p o stereo full-bridge thd+n < 10% thd+n < 1% - - 0.23 0.19 - - w rms w rms mono parallel full-bridge thd+n < 10% thd+n < 1% - - 0.44 0.35 - - w rms w rms total harmonic distortion + noise thd+n stereo full-bridge p o = 0 dbfs = 0.18 w - 0.50 - % mono parallel full-bridge p o = -3 dbfs = 0.17 w p o = 0 dbfs = 0.35 w - - 0.08 0.43 - - % % dynamic range dr stereo full-bridge p o = -60 dbfs, a-weighted p o = -60 dbfs, unweighted - - 91 88 - - db db mono parallel full-bridge p o = -60 dbfs, a-weighted p o = -60 dbfs, unweighted - - 94 91 - - db db mosfet on resistance r ds(on) vp = 5.0v, i d = 0.5 a - 600 - m mosfet on resistance r ds(on) vp = 3.7v, i d = 0.5 a - 640 - m mosfet on resistance r ds(on) vp = 2.5v, i d = 0.5 a - 760 - m efficiency vp = 5.0 v, p o = 2 x 0.8 w, r l = 8 -82-% output operating peak current i pc --1.5a parameters va = 2.5v min typ max va = 1.8v min typ max unit aoutx voltage into r l = 10 k hp_gain[2:0] analog gain (g) vhp 000 0.3959 1.8 v - 1.34 - - 0.97 - v pp 2.5 v - 1.34 - - 0.97 - v pp 001 0.4571 1.8 v - 1.55 - - 1.12 - v pp 2.5 v - 1.55 - - 1.12 - v pp 010 0.5111 1.8 v - 1.73 - - 1.25 - v pp 2.5 v - 1.73 - - 1.25 - v pp 011 (default) 0.6047 1.8 v - 2.05 - 1.41 1.48 1.55 v pp 2.5 v 1.95 2.05 2.15 - 1.48 - v pp 100 0.7099 1.8 v - 2.41 - - 1.73 - v pp 2.5 v - 2.41 - - 1.73 - v pp 101 0.8399 1.8 v - 2.85 - 2.05 v pp 2.5 v - 2.85 - - 2.05 - v pp 110 1.0000 1.8 v - 3.39 - - 2.44 - v pp 2.5 v - 3.39 - - 2.44 - v pp 111 1.1430 1.8 v (see (note 11) 2.79 v pp 2.5 v - 3.88 - - 2.79 - v pp parameters (note 10) symbol conditions min typ max units
ds680a1 19 CS42L52 headphone output po wer characteristics test conditions (unless otherwise specifi ed): input test signal is a full-scale 997 hz sine wave; measurement bandwidth is 10 hz to 20 khz; sample frequency = 48 khz; test load r l = 16 , c l = 10 pf (see figure 2 ). 11. vhp settings lower than va reduces the headroom of the headphone amplifier. as a result, the dac may not achieve the full thd+n performance at full-scale output voltage and power. parameters va = 2.5v min typ max va = 1.8v min typ max unit aoutx power into r l = 16 hp_gain[2:0] analog gain (g) vhp 000 0.3959 1.8 v - 14 - - 7 - mw rms 2.5 v - 14 - - 7 - mw rms 001 0.4571 1.8 v - 19 - - 10 - mw rms 2.5 v - 19 - - 10 - mw rms 010 0.5111 1.8 v - 23 - - 12 - mw rms 2.5 v - 23 - - 12 - mw rms 011 (default) 0.6047 1.8 v (note 11) -17 -mw rms 2.5 v - 32 - - 17 - mw rms 100 0.7099 1.8 v (note 11) -23 -mw rms 2.5 v - 44 - - 23 - mw rms 101 0.8399 1.8 v (note 7) see figure 22 on page 75 mw rms 2.5 v -32 -mw rms 110 1.0000 1.8 v ( note 7 , 11 ) see figures 22 and 23 on page 75 mw rms 2.5 v mw rms 111 1.1430 1.8 v mw rms 2.5 v mw rms aoutx agnd r l c l 0.022 f 51 figure 2. headphone output test load
20 ds680a1 CS42L52 combined dac interp olation & on-chip ana log filter response 12. response is clock dependent and will scale wi th fs. note that the response plots ( figures 30 and 33 on page 79 ) have been normalized to fs and can be de-normaliz ed by multiplying the x-axis scale by fs. 13. measurement bandwidth is from stopband to 3 fs. parameters (note 12) min typ max unit frequency response 10 hz to 20 khz -0.01 - +0.08 db passband to -0.05 db corner to -3 db corner 0 0 - - 0.4780 0.4996 fs fs stopband 0.5465 - - fs stopband attenuation (note 13) 50 - - db group delay - 9/fs - s de-emphasis error fs = 32 khz fs = 44.1 khz fs = 48 khz - - - - - - +1.5/+0 +0.05/-0.25 -0.2/-0.4 db db db
ds680a1 21 CS42L52 switching specifications - serial port (inputs: logic 0 = dgnd, logic 1 = vl, sdout c load = 15 pf.) 14. after powering up the CS42L52, reset should be held low after the power supplies and clocks are settled. 15. see ?example system clock frequencies? on page 77 for typical mclk frequencies. parameters symbol min max units reset pin low pulse width (note 14) 1-ms mclk frequency (note 15) (see ?serial port clock- ing? on page 34 ) mhz mclk duty cycle 45 55 % slave mode input sample rate (lrck) f s (see ?serial port clock- ing? on page 34 ) khz lrck duty cycle 45 55 % sclk frequency 1/t p - 64?f s hz sclk duty cycle 45 55 % lrck setup time before sclk rising edge t s(lk-sk) 40 - ns lrck edge to sdout msb output delay t d(msb) -52ns sdout setup time before sclk rising edge t s(sdo-sk) 20 - ns sdout hold time afte r sclk rising edge t h(sk-sdo) 30 - ns sdin setup time before sclk rising edge t s(sd-sk) 20 - ns sdin hold time after sclk rising edge t h 20 - ns master mode output sample rate (lrck) all speed modes f s (see ?serial port clock- ing? on page 34 ) hz lrck duty cycle 45 55 % sclk frequency sclk=mclk mode 1/t p - 12.0000 mhz mclk=12.0000 mhz 1/t p - 68?f s hz all other modes 1/t p - 64?f s hz sclk duty cycle 45 55 % lrck edge to sdout msb output delay t d(msb) -52ns sdout setup time before sclk rising edge t s(sdo-sk) 20 - ns sdout hold time afte r sclk rising edge t h(sk-sdo) 30 - ns sdin setup time before sclk rising edge t s(sd-sk) 20 - ns sdin hold time after sclk rising edge t h 20 - ns t h(sk-sdo) // // // // // // // // t s(sd-sk) msb msb msb-1 msb-1 lrck sclk sdout sdin t d(msb) t s(lk-sk) t p t h t s(sdo-sk) figure 3. serial audio interface timing
22 ds680a1 CS42L52 switching specifications - i2c control port (inputs: logic 0 = dgnd, logic 1 = vl, sda c l =30pf) 16. data must be held for sufficient ti me to bridge the transition time, t fc , of scl. parameters symbol min max unit scl clock frequency f scl - 100 khz reset rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 16) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of scl and sda t rc -1s fall time scl and sda t fc - 300 ns setup time for stop condition t susp 4.7 - s acknowledge delay from scl falling t ack 300 1000 ns t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop start start stop repeated sda scl t irs rst figure 4. control port timing - i2c
ds680a1 23 CS42L52 dc electrical characteristics (agnd = 0 v; all voltages with respect to ground.) 17. valid with the recommended capa citor values on filt + and vq. increasing the capacitance will also increase the psrr. 18. the pga is biased with vq, created from a resistor divider from the va supply. increasing the capaci- tance on vq will also increase th e psrr at low frequencies. a 10 f capacitor on vq improves the psrr to 42 db. digital interface specific ations & characteristics 19. see ?i/o pin characteristics? on page 9 for serial and control port power rails. parameters min typ max units vq characteristics nominal voltage output impedance dc current source/sink - - - 0.5?va 23 - - - 1 v k a mic bias characteristics nominal voltage micbias_lvl[1:0] = 00 micbias_lvl[1:0] = 01 micbias_lvl[1:0] = 10 micbias_lvl[1:0] = 11 dc output current power supply rejection ratio (psrr) 1 khz - - - - - - 0.8?va 0.7?va 0.6?va 0.5?va - 50 - - - - 1 - v v v v ma db power supply rejection ratio characteristics psrr @1 khz (note 17) pga to adc adc dac (hp & line amps) - - - 44 60 60 - - - db db db psrr @60 hz (note 17) pga to adc (note 18) adc dac (hp & line amps) - - - 22 42 60 - - - db db db psrr @217 hz full-bridge pwm outputs - 56 - db parameters (note 19) symbol min max units input leakage current i in -10 a input capacitance -10pf 1.8 v - 3.3 v logic high-level output voltage (i oh = -100 a) v oh vl - 0.2 - v low-level output voltage (i ol = 100 a) v ol -0.2v high-level input voltage vl = 1.65 v vl = 1.8 v vl = 2.0 v vl > 2.0 v v ih 0.83?vl 0.76?vl 0.68?vl\ 0.65?vl -v low-level input voltage v il -0.35?vlv
24 ds680a1 CS42L52 power consumption see (note 20) . 20. unless otherwise noted, test conditions are as follows: all zeros input, sl ave mode, sample rate = 48 khz; no load. digital (vd) and logic (vl) supply current will vary depending on speed mode and mas- ter/slave operation. 21. reset pin 25 held lo, all clocks and data lines are held lo. 22. reset pin 25 held hi, all clocks and data lines are held hi. 23. vl current will slightly increase in master mode. power ctl. registers typical current (ma) operation 02h 03h 04h pdn_pgab pdn_pgaa pdn_adcb pdn_adca pdn pdn_micb pdn_mica pdn_micbias pdn_hpb[1:0] pdn_hpa[1:0] pdn_spkb[1:0] pdn_spka[1:0] v i vhp i va i vd i vl vl=3.3v (note 23) i vp vp=3.7v total power (mw rms ) 1 off (note 21) xxxxxxxxx x x x 1.8 0.00 0.00 0.00 0.00 0.00 0.00 2.5 0.00 0.00 0.00 0.00 2 standby (note 22) xxxx1xxxx x x x 1.8 0.00 0.00 0.01 0.00 0.00 0.02 2.5 0.00 0.00 0.02 0.05 3 mono record adc1110011111111111 1.8 0.00 1.67 2.32 0.03 0.00 7.24 2.5 0.00 1.87 3.72 14.05 pga to adc1010011111111111 1.8 0.00 2.1 2.31 0.03 0.00 7.99 2.5 0.00 2.3 3.72 15.13 mic to pga to adc (with bias) 1010010011111111 1.8 0.00 3.48 2.32 0.03 0.00 10.49 2.5 0.00 3.71 3.72 18.65 mic to pga to adc (no bias) 1010010111111111 1.8 0.00 3.15 2.32 0.03 0.00 9.90 2.5 0.00 3.37 3.73 17.83 4 stereo record adc1100011111111111 1.8 0.00 2.31 2.37 0.03 0.00 8.48 2.5 0.00 2.53 3.82 15.95 pga to adc0000011111111111 1.8 0.00 3.18 2.37 0.03 0.00 10.04 2.5 0.00 3.42 3.81 18.15 mic to pga to adc (no bias) 0000000111111111 1.8 0.00 5.32 2.37 0.03 0.00 13.90 2.5 0.00 5.57 3.81 23.53 5 mono playback to headphone 1111011110111111 1.8 1.59 1.99 2.72 0.01 0.00 11.36 2.5 2.07 2.62 4.27 22.43 6 mono playback to speaker 1111011111111010 1.8 0.00 0.20 4.42 0.01 3.30 20.54 2.5 0.00 0.22 6.77 29.71 7 stereo playback to headphone 1111011110101111 1.8 2.77 2.00 2.91 0.01 0.00 13.84 2.5 3.27 2.63 4.28 25.48 8 stereo playback to speaker 1111011111111010 1.8 0.00 0.20 4.38 0.01 3.30 20.47 2.5 0.00 0.22 6.80 29.79 9 stereo passthru to headphone 1111011110101111 1.8 2.79 1.91 1.06 0.01 0.00 10.39 2.5 3.18 2.14 1.81 17.85 10 mono record & playback pga in (no mic) to mono hp 1010011111101111 1.8 1.77 3.95 4.28 0.03 0.00 18.05 2.5 2.13 4.77 6.63 33.90 11 phone monitor mic (w/bias) in to mono out 1010010011101111 1.8 1.76 5.33 4.28 0.03 0.00 20.52 2.5 2.15 6.19 6.69 37.65 12 stereo record & playback pga in (no mic) to st. hp out 0000011110101111 1.8 2.76 5.05 4.64 0.03 0.00 22.46 2.5 3.21 5.90 7.17 40.78 13 stereo rec. & full playback pga (no mic) to st. hp & spk 0000011110101010 1.8 3.49 5.24 7.20 0.03 3.30 40.94 2.5 3.95 6.10 10.46 63.56
ds680a1 25 CS42L52 4. applications 4.1 overview 4.1.1 basic architecture the CS42L52 is a highly integrated, low power, 24-bit audio codec compris ed of a stereo analog-to- digital converter (adc), a stereo digital-to-analog converter (dac), a digital pwm modulator and two full- bridge power back-ends. the adc and dac are desi gned using multi-bit delta-sigma techniques - the dac operates at an oversampling ratio of 128fs and the adc operates at 64fs, where fs is equal to the system sample rate. the different clock rates maximize power savings while maintaining high performance. the pwm modu- lator operates at a fixed frequency of 384 khz. the po wer fets are configured fo r either stereo full-bridge or mono parallel full bridge output. the codec operates in one of four sample rate speed modes: quar- ter, half, single and double. it accepts and is capab le of generating serial port clocks (sclk, lrck) de- rived from an input master clock (mclk). 4.1.2 line & mic inputs the analog input portion of the code c allows selection from and configuration of multiple combinations of stereo and microphone (mic) sources. eight line inputs with an option for two balanced mic inputs, a mic bias output and a programmable gain amp lifier (pga) comprise the analog front-end. 4.1.3 line & headphone outputs the analog output portion of the codec includes a headphone amplifier capable of driving headphone and line-level loads. an on-chip charge pump creates a negative headphone supply allowing a full-scale output swing centered around ground. this eliminates the need for larg e dc-blocking capacitors and al- lows the amplifier to deliver more power to headphone loads at lower supply voltages. 4.1.4 speaker driver outputs the class d power amplifiers drive 8 ohm (stereo) and 4 ohm (mono) speakers directly, without the need for an external filter. the power mosfets are powere d directly from a battery eliminating the efficiency loss associated with an external regulator. battery level monitoring and compensation maintains a steady output as battery levels fall. a temperature monitor continually measures the die temperature and regis- ters when predefined thresholds are exceeded. note : the CS42L52 should only be used in captive speaker systems where the outputs are pe rmanently tied to the speaker terminals. 4.1.5 fixed function dsp engine the fixed-function digital signal processing engine processes both the pcm serial input data and adc output data, allowing a mix between the two. indepen dent volume control, left/right channel swaps, mono mixes, tone control and limiting functions also comprise the dsp engine. 4.1.6 beep generator the beep generator delivers tones at select frequen cies across approximately two octave major scales. with independent volume control, beeps may be config ured to occur continuously, periodically, or at sin- gle time intervals. 4.1.7 power management three control registers provide independent power-dow n control of the adc, dac, pga, mic pre-amp, mic bias, headphone and speaker outputs, allowing o peration in select applications with minimal power consumption.
26 ds680a1 CS42L52 4.2 analog inputs referenced control register location analog front end pdn_pgax ......................... pgaxvol[5:0]..................... adcb=a .............................. anlgsftx .......................... anlgzcx ............................ adcxsel[2:0] ..................... pgaxsel5,4,3,2,1 .............. biaslvl[2:0] ....................... pdn_bias........................... pdn_adcx ......................... pdn_chrg ........................ inv_adcx ........................... hpfrzx............................... hpfx ................................... hpfx_cf[1:0]...................... adcxovfl.......................... digital volume adcxmute......................... adcxvol............................ alcx.................................... alcxsrdis......................... alcxzcdis......................... alcarate[5:0]................... alcrrate[5:0] .................. max[2:0].............................. min[2:0]............................... ngall................................. ng ....................................... thresh[3:0]....................... ngdelay[1:0] .................... miscellaneous digsum[1:0] ....................... digmux .............................. ?power down pgax? on page 42 ?pgax volume? on page 56 ?adc channel b=a? on page 50 ?ch. x analog soft ramp? on page 49 ?ch. x analog zero cross? on page 49 ?adc input select? on page 48 ?pga input mapping? on page 49 ?mic bias level? on page 48 ?power down mic bias? on page 43 ?power down adcx? on page 43 ?power down adc charge pump? on page 42 ?invert adc signal polarity? on page 50 ?adcx high-pass filter freeze? on page 49 ?adcx high-pass filter? on page 49 ?hpf x corner frequency? on page 50 ?adcx overflow (read only)? on page 71 ?adc mute? on page 51 ?adcx volume? on page 57 ?alcx enable? on page 67 ?alcx soft ramp disable? on page 55 ?alcx zero cross disable? on page 55 ?alc attack rate? on page 67 ?alc release rate? on page 68 ?alc maximum threshold? on page 68 ?alc minimum threshold? on page 69 ?noise gate all channels? on page 69 ?noise gate enable? on page 69 ?noise gate threshold and boost? on page 70 ?noise gate delay timing? on page 70 ?digital sum? on page 50 ?digital mux? on page 50 ` ain4a/ mic1+/ mic2a gain adjust alc pdn_pgaa pgaavol[5:0] adcb=a anlgsfta anlgzca hpfrza hpfa hpfa_cf[1:0] pdn_adca inv_adca pdn_chrg alcb alcbsrdis alcbzcdis micbias biaslvl[2:0] pdn_bias pcm serial interface to dsp engine alcarate[5:0] alcrrate[5:0] max[2:0] min[2:0] alca alcasrdis alcazcdis ain1a ain2a = pgaasel[5:1] adc pdn_pgab pgabvol[5:0] adcb=a anlgsftb anlgzcb adcbmute digsft digzc adcbvol[7:0] +24/-96db 1db steps hpfrzb hpb hpfb_cf[1:0] pdn_adcb inv_adcb pdn_chrg noise gate ngall ng thresh[3:0] ngdelay[1:0] gain adjust from dsp engine digmix ain3a/mic1-/ mic1a ain4b/ mic2+/ mic2b ain1b ain2b ain3b/mic2-/ mic1b analog pass thru to headphone amplifier mux swap/ mix digsum[1:0] adcamute digsft digzc adcavol[7:0] +24/-96db 1db steps refer to ?mic inputs? adc adcasel[2:0] adcbsel[2:0] = pgabsel[5:1] refer to ?mic inputs? figure 5. analog input signal flow
ds680a1 27 CS42L52 4.2.1 mic inputs the input pins 21, 22, 23 and 24 accept stereo line-level or microphone signals. for microphone inputs, either single-ended or differential configuration is allowed, providing programmable pre-amplification of low-level signals. in the single-ended configuration, an internal mux chooses one of two stereo sets (se- lection is made independently on channels a and b). in the differential configurat ion, an internal voltage follower cascaded with the pre-amplifier maintains high input impedance and provides noise rejection above the micxgain setting. the pre-amps are biased to vq in both configurations. 4.2.2 automatic level control (alc) when enabled, the alc monitors the analog input signal after the digital attenuator, detects when peak levels exceed the maximum threshold settings and lowe rs, first, the pga gain settings and then increases the digital attenuation levels at a programmable attack rate and maintains the resulting level below the maximum threshold. when input signal levels fall below the minimum threshold, digital atte nuation levels are decreased first and the pga gain is then increased at a programma ble release rate and maintains the resulting level above the minimum threshold. attack and release rates are affected by the adc soft ramp/zero cross settings and sample rate, fs. alc soft ramp and zero cross dependency may be independently enabled/disabled. recommended settings : best level control may be realized with the fastest attack and slowest release setting with soft ramp enabled in the control registers. notes: 1. when alc x is enabled and the pgaxvol[5:0] is set above 12 db, the adcxvol[7:0] should not be set below 0 db. 2. the maximum realized gain must be set in the pgaxvol register. the alc will only apply the gain set in the pgaxvol. 3. the alc maintains the output signal between the min and max thresholds. as the input signal level changes, the level-controlled out put may not always be the sa me but will always fall within the thresholds. referenced control register location micxcfg ............................ pdn_micx .......................... micxgain ........................... ?micx configuration? on page 55 ?power down micx? on page 43 ?micx gain? on page 55 referenced contro l register location pgaxvol[5:0 max[2:0], min[2:0] ?pgax vol. & alcx transition ctl.: alc, pga a (address 12h) & alc, pga b (address 13h)? on page 55 ?alc threshold (address 2ch)? on page 68 mic1- - + - + mic1+ mic2- - + - + mic2+ 23 21 24 22 micacfg=?1'b micbcfg=?1'b micagain[4:0] micbgain[4:0] 16..32 db/ 1 db steps 16..32 db/ 1 db steps pdn_mica=?0'b pdn_micb=?0'b to summing pga a note : output to pga = (mic + - mic - )*gain + mic - to summing pga b mic1a - + mic2a mic1b - + mic2b 23 21 24 22 micacfg=?0'b micbcfg=?0'b micagain[4:0] micbgain[4:0] 16..32 db/ 1 db steps 16..32 db/ 1 db steps pdn_mica=?0'b pdn_micb=?0'b micasel micbsel to summing pga a to summing pga b vq vq figure 6. single-ended mic configuration f igure 7. differential mic configuration
28 ds680a1 CS42L52 4.2.3 noise gate the noise gate may be used to mute signal levels th at fall below a programmable threshold. this prevents the alc from applying gain to noise. a programmable delay may be used to set the minimum time before the noise gate attacks the signal. note: maximum noise gate atte nuation levels will depen d on the gain applied in either the pga or mic pre-amplifier. for example: if both +32 db pre-am plification and +12 db programmable gain is applied, the maximum attenuation that the no ise gate achieves will be 52 db (- 96 + 32 + 12) below full-scale. referenced control register location noise gate controls............ ?noise gate control (address 2dh)? on page 69 output (after alc) input rrate[5:0] pga gain and/or attenuator alc max[2:0] arate[5:0 ] below full scale min[2:0] below full scale min[2:0] below full scale max[2:0] below full scale figure 8. alc -96 -40 thresh[2:0] maximum attenuation* -52 db output (db) input (db) n g e n = 1 n g e n = 0 -80 db -64 db figure 9. noise gate attenuation
ds680a1 29 CS42L52 4.3 analog outputs referenced control register location dsp deemph ............................. pmixxmute........................ pmixxvol[6:0].................... inv_pcmx........................... pcmxswap[1:0] ................. amixxmute........................ amixxvol[6:0].................... adcxswap[1:0].................. mstxvol[7:0]..................... mstxmute......................... digsft ............................... digzc ................................. plybckb=a........................ tc_en................................. bass_cf[1:0] ..................... treb_cf[1:0] ..................... bass[3:0]............................ treb[3:0]............................ limit ................................... limsrdis ........................... limzcdis............................ lmax[2:0]............................ cush[2:0] ........................... limarate[7:0].................... limrrate[7:0] ................... ?hp/speaker de-emphasis? on page 52 ?pcm mixer channel x mute? on page 58 ?pcm mixer channel x volume? on page 58 ?invert pcm signal polarity? on page 51 ?pcm mix channel swap? on page 64 ?adc mixer channel x mute? on page 58 ?adc mixer channel x volume? on page 58 ?adc mix channel swap? on page 64 ?master volume control? on page 63 ?master playback mute? on page 51 ?digital soft ramp? on page 53 ?digital zero cross? on page 53 ?playback volume setting b=a? on page 51 ?tone control enable? on page 62 ?bass corner frequency? on page 62 ?treble corner frequency? on page 62 ?bass gain? on page 63 ?treble gain? on page 62 ?peak detect and limiter? on page 66 ?limiter soft ramp disable? on page 65 ?limiter zero cross disable? on page 66 ?limiter maximum threshold? on page 65 ?limiter cushion threshold? on page 65 ?limiter attack rate? on page 67 ?limiter release rate? on page 66 beep generator vol bass/ treble/ control vol peak detect limiter chnl vol. settings channel swap demph vol vol +12db/-102db 0.5db steps mstavol[7:0] mstbvol[7:0] +12db/-51.5db 0.5db steps amixamute amixbmute amixavol[6:0] amixbvol[6:0] +12db/-51.5db 0.5db steps pmixamute pmixbmute pmixavol[6:0] pmixbvol[6:0] 0db/-50db 2.0db steps bpvol[4:0] deemph tc_en bass_cf[1:0] treb_cf[1:0] bass[3:0] treb[3:0] +12.0db/-10.5db 1.5db steps fixed function dsp mstamute mstbmute digsft digzc plybckb=a limarate[7:0] limrrate[7:0] lmax[2:0] cush[2:0] limsrdis limzcdis limit pcmaswap[1:0] pcmbswap[1:0] pcm serial interface inputs from adca and adcb offtime[2:0] ontime[3:0] freq[3:0] beep[1:0] beepmixdis digital mix to adc serial interface channel swap inv_pcma inv_pcmb adcaswap[1:0] adcbswap[1:0] pwm modulator dac figure 10. dsp engine signal flow
30 ds680a1 CS42L52 4.3.1 beep generator the beep generator generates audio frequencies acro ss approximately two octave major scales. it offers three modes of operation: continuous, multiple and si ngle (one-shot) beeps. sixteen on and eight off times are available. note: the beep is generated before the limiter and may affect desired limiting pe rformance. if the lim- iter function is used, it may be required to set the b eep volume sufficiently below the threshold to prevent the peak detect from triggering. sinc e the master volume control, mstx vol[7:0], will affect the beep vol- ume, dac volume may alternatively be controlled using the pmixxvol[6:0] bits. referenced contro l register location pwm control spkxmute ......................... mute50/50 ......................... spkmono .......................... spkxvol[7:0] ..................... spkswap........................... spkb=a .............................. battcmp ........................... vpref[3:0] ......................... vplvl[7:0] .......................... thrfld .............................. spkattn[2:0] ..................... pdn_spkx[1:0]................... release............................ twrn.................................. terr................................... spkxshrt.......................... ?speaker mute? on page 53 ?speaker mute 50/50 control? on page 54 ?speaker mono control? on page 54 ?speaker volume control? on page 64 ?speaker channel swap? on page 54 ?speaker volume setting b=a? on page 54 ?battery compensation? on page 71 ?vp reference? on page 72 ?vp voltage level (read only)? on page 72 ?thermal foldback? on page 73 ?speaker attenuation? on page 74 ?speaker power control? on page 44 ?temperature acknowledge & release? on page 73 ?thermal warning status (read only)? on page 73 ?thermal error status (read only)? on page 73 ?speaker current load status (read only)? on page 72 referenced contro l register location analog output hpxmute ........................... hpxvol[7:0] ....................... pdn_hpx[1:0] ..................... hpgain[2:0]........................ passthrux ....................... passxmute ....................... passxvol[7:0] ................... chgfreq .......................... ?headphone mute? on page 53 ?headphone volume control? on page 63 ?headphone power control? on page 44 ?headphone analog gain? on page 51 ?passthru analog? on page 52 ?passthru mute? on page 52 ?passthru x volume? on page 56 ?charge pump frequency? on page 74 charge pump dac chgfreq[3:0] hpgain[2:0] vol vol analog passthru from pga hpamute hpbmute hpa_vol[7:0] hpb_vol[7:0] +0db/-102db 0.5db steps passamute passbmute passavol[7:0] passbvol[70] +12db/-60db 0.5db steps (uses pga) passt hrua passt hrub pdn_hpa[1:0] pdn_hpb[1:0] a b from dsp engine hp/line outputs vol pwm modulator a spkamute spkbmute mute50/50 spkmono spkswap spkb=a spkavol[7:0] spkbvol[7:0] +0db/-102db 0.5db steps pdn_spka[1:0] pdn_spkb[1:0] release thermal monitor short circuit spkashrt twrn terr thermal foldback thrfld spkattn[2:0] battery compensation battcmp vpref[3:0] vplvl[7:0] spkbshrt + - + - gate drive from dsp engine speaker outputs b figure 11. pwm output stage figure 12. analog output stage
ds680a1 31 CS42L52 4.3.2 limiter when enabled, the limiter monitors the digital inpu t signal before the dac and pwm modulators, detects when levels exceed the maximum threshold settings and lowers the master volume at a programmable attack rate below the maximum thre shold. when the input signal level falls below the maximum threshold, the aout volume returns to its orig inal level set in the master volume control register at a programmable release rate. attack and release rates are affected by the dac soft ramp/zero cross settings and sample rate, fs. limiter soft ramp and zero cross depe ndency may be independent ly enabled/disabled. notes: 1. recommended settings : best limiting performance may be realized with the fastest attack and slowest release setting with soft ramp enabled in the control registers. the min bits allow the user to set a threshold slightly below the maximum threshold for hysteresis control - this cushions the sound as the limiter attacks and releases. 2. the limiter maintains the output signal between the min and max thresholds. as the digital input signal level changes, the level-c ontrolled output may not always be the same but will always fall within the thresholds. referenced contro l register location mstxvol[7:0]..................... pmixxvol[6:0] ................... offtime[2:0] ..................... ontime[3:0] ....................... freq[3:0] ........................... beep[1:0]............................ beepmixdis ...................... bpvol[4:0] ......................... ?master volume control: msta (address 20h) & mstb (address 21h)? on page 63 ?pcmx mixer volume: pcma (address 1ah) & pcmb (address 1bh)? on page 58 ?beep off time? on page 60 ?beep on time? on page 60 ?beep frequency? on page 59 ?beep configuration? on page 61 ?beep mix disable? on page 61 ?beep volume? on page 61 referenced contro l register location limiter controls ................... master volume control........ ?limiter control 2, release rate (address 28h)? on page 66 , ?limiter attack rate (address 29h)? on page 67 ?master volume control: msta (address 20h) & mstb (address 21h)? on page 63 freq[3:0] ... bpvol[4:0] ontime[3:0] offtime[2:0] beep[1:0] = '01' beep[1:0] = '10' beep[1:0] = '11' single-beep : beep turns on at a configurable frequency (freq) and volume (bpvol) for the duration of ontime. beep must be cleared and set for additional beeps. multi-beep : beep turns on at a configurable frequency (freq) and volume (bpvol) for the duration of ontime and turns off for the duration of offtime. on and off cycles are repeated until beep is cleared. continuous beep : beep turns on at a configurable frequency (freq) and volume (bpvol) and remains on until beep is cleared. figure 13. beep configuration options
32 ds680a1 CS42L52 4.4 analog in to analog out passthru the CS42L52 accommodates analog routin g of the analog input signal dire ctly to the headphone amplifiers. this feature is useful in applications that utilize an fm tuner wh ere audio recovered ov er-the-air must be transmitted to the headphone amplifier without digital co nversion in the adc and dac. this analog passthru path reduces power consumption and is immune to modulator switching noise that could interfere with some tuners. 4.4.1 overriding the adc power down to accommodate automatic activation of the speake r amplifier when the spk/hp_sw switch pin chang- es, the CS42L52 provides the option to automatically power up the adc whenever the analog signal must route to the digital pwm modulator, regardless of the pdn_adc bit. refer to the table below for how this adc power-down override functions in accord with t he state of the speaker channels. the shaded cells represent normal adc operation when passthru is disabled. when passthru and pdn_ovrd are en abled, turning the speaker channel on (by writing ?11?b to spkx_pdn[1:0] or by automatic acti vation of the hea dphone detect switch, spk/ hp_sw) will automati- cally disable the adcx_pdn in order to convert the analog input to a di gital signal for the pwm modulator. this allows automatic an alog input routing to the speaker amplifiers. pdn_adc passthru pdn_ovrd speaker channel adc status 0 x x x powered up 1 0 x x powered down 1 0 x powered down 1 off powered down on powered up max[2:0] output (after limiter) input rrate[5:0] arate[5:0] volume limiter cush[2:0] attack/release sound cushion max[2:0] fi g ure 14. peak detect & limiter
ds680a1 33 CS42L52 4.4.2 overriding the pga power down to accommodate automatic activa tion of the headphone amplifier when the spk/hp_sw switch pin changes, the CS42L52 will aut omatically power up t he pga whenever passthru is enabled, regardless of the pdn_pga setting. refer to the table below for how this pga power-down override functions in accord with the state of the headphone channels. the shaded cells represent normal pga operation when passthru is disabled. when passthru is enabled, turning the headphone ch annel on (by writing ?11?b to hpx_pdn[1:0] or by automatic activation of the headphone detect switch, spk/hp_sw) will automatically disable the pgax_pdn in order to transmit the analog signal to the headphone. 4.5 pwm outputs 4.5.1 mono speaker output configuration the CS42L52 accommodates a stereo as well as a mo no speaker output configuration. in mono mode the output drivers of each channel are connected in parallel to deliver maximum power to a 4 ohm speak- er. refer to the table below for pin mapping in mono configuration. 4.5.2 vp battery compensation the CS42L52 provides the option to maintain a desired power output level, independent of the vp supply. when enabled, this feature works by monitoring the voltage on the vp supply and reducing the attenua- tion on the speaker outputs when vp voltage levels fall. note: the internal adc that monitors the vp supply operates from the va supply. calculations are based on typ- ical va levels of 1.8 v and 2.5 v using the vpref bits. referenced contro l register location pdn_adcx ......................... passthru ......................... pdn_ovrd ........................ spkx_pdn[1:0]................... ?power down adcx? on page 43 ?passthru analog? on page 52 ?power down adc override? on page 43 ?speaker power control? on page 44 pdn_pga passthru hp channel pga status 0 x x powered up 1 0 x powered down 1 off powered down on powered up referenced contro l register location pdn_pgax ......................... passthru ......................... hpx_pdn[1:0]..................... ?power down pgax? on page 42 ?passthru analog? on page 52 ?headphone power control? on page 44 pin speaker output spkmono=0 spkmono=1 spkswap=0 spkswap=1 spkswap=0 spkswap=1 4 spkouta+ spkoutb+ spkouta+ spkoutb+ 6 spkouta- spkoutb- spkouta+ spkoutb+ 7 spkoutb+ spkouta+ spkouta- spkoutb- 9 spkoutb- spkouta- spkouta- spkoutb- referenced contro l register location spkmono.......................... spkswap........................... ?speaker mono control? on page 54 ?speaker channel swap? on page 54
34 ds680a1 CS42L52 4.5.2.1 maintaining a desired output level using spkxvol, the speaker ou tput level must first be attenuated by the decibel equivalent of the expect- ed vp supply range (max relative to min). the CS42L52 then gradually reduces the attenuation as the vp supply drops from it?s maximum level, ma intaining a nearly constant power output. compensation example 1 (vp battery supply ranges from 4.5 v to 3.0 v) 1. set speaker attenuation (spkxvol) to -3.5 db. the vp supply changes ~3.5 db. 2. set the reference vp supply (vpref) to 4.5 v. 3. enable battery compensation (battcmp). the CS42L52 automatically adjusts the output level as the battery discharges. compensation example 2 (vp battery supply ranges from 5.0 v to 1.6 v) 1. set speaker attenuation (spkxvol) to -10 db. the vp supply changes ~9.9 db. 2. set the reference vp supply (vpref) to 5.0 v. 3. enable battery compensation (battcmp). the CS42L52 automatically adjusts the output level as the battery discharges. refer to figure 15 on page 34 . in this example, the vp supply changes over a wide range, illu strating the accuracy of the CS42L52?s battery compensation. 4.6 serial port clocking the codec serial audio interface port operates ei ther as a slave or master, determined by the m/s bit. it accepts externally generated clocks in slave mode and w ill generate synchronous clocks derived from an input master clock (mclk) in master mode. refer to the tables below for the required setting in register 05h and 06h associated with a given mclk and sample rate. referenced control register location vpref ................................ spkxvol ............................ ?vp reference? on page 72 ?speaker volume control? on page 64 referenced control register location m/s register 05h register 06h ?master/slave mode? on page 46 ?clocking control (address 05h)? on page 44 ?interface control 1 (address 06h)? on page 46 -24 -22 -20 -18 -16 -14 -12 -10 -8 -6 1.6 1.9 2.2 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 uncompensated pwm output level battery compensated pwm output level vp supply (v) pwm output level (db) figure 15. battery compensation
ds680a1 35 CS42L52 mclk (mhz) sample rate, fs (khz) speed[1:0] (auto=?0?b ) 32kgroup videoclk ratio[1:0] mclkdiv2 12.2880 8.0000 11 1 0 00 0 12.0000 11 0 0 00 0 16.0000 10 1 0 00 0 24.0000 10 0 0 00 0 32.0000 01 1 0 00 0 48.0000 01 0 0 00 0 96.0000 00 0 0 00 0 11.2896 11.0250 11 0 0 00 0 22.0500 10 0 0 00 0 44.1000 01 0 0 00 0 88.2000 00 0 0 00 0 18.4320 8.0000 11 1 0 00 0 12.0000 11 0 0 00 0 16.0000 10 1 0 00 0 24.0000 10 0 0 00 0 32.0000 01 1 0 00 0 48.0000 01 0 0 00 0 96.0000 00 0 0 00 0 16.9344 8.0182 11 0 0 10 0 11.0250 11 0 0 00 0 22.0500 10 0 0 00 0 44.1000 01 0 0 00 0 88.2000 00 0 0 00 0 12.0000 8.0000 11 1 0 01 0 11.029411 0 0110 12.0000 11 0 0 01 0 16.0000 10 1 0 01 0 22.058810 0 0110 24.0000 10 0 0 01 0 32.0000 01 1 0 01 0 44.117601 0 0110 48.0000 01 0 0 01 0 88.235300 0 0110 96.0000 00 0 0 01 0 24.0000 8.0000 11 1 0 01 1 11.029411 0 0111 12.0000 11 0 0 01 1 16.0000 10 1 0 01 1 22.058810 0 0111 24.0000 10 0 0 01 1 32.0000 01 1 0 01 1 44.117601 0 0111 48.0000 01 0 0 01 1 88.235300 0 0111 96.0000 00 0 0 01 1 27.0000 8.0000 11 1 1 01 0 12.0000 11 0 1 01 0 24.0000 10 0 1 01 0 32.0000 01 1 1 01 0 44.117601 0 1110 48.0000 01 0 1 01 0 11.029411 0 1110 22.058810 0 1110 16.0000 10 1 1 01 0 table 1. mclk, lrck quick decode
36 ds680a1 CS42L52 4.7 digital interface formats the serial port operates in standard i2s, left-justified, right-justified (dac only), or dsp mode digital in- terface formats with varying bit depths from 16 to 24. data is clocked out of the adc or into the dac on the rising edge of sclk. 4.7.1 dsp mode in dsp mode, the lrck acts as a frame sync for 2 data-packed words (left and right channel) input on sdin and output on sdout. the msb is input/output on the first sclk rising edge after the frame sync rising edge. the right channel immediately follows the left channel. 4.8 initialization the codec enters a power-do wn state upon initial powe r-up. the interpolation and decimation filters, del- ta-sigma and pwm modulators and control port registers are reset. the internal voltage reference, and switched-capacitor low-pass filters are powered down. lrck sclk msb lsb msb lsb aouta / ainxa left channel right channel sdout sdin aoutb / ainxb msb figure 16. i2s format lrck sclk msb lsb msb lsb left channel right channel sdout sdin msb aouta / ainxa aoutb / ainxb figure 17. left-justified format lrck sclk msb lsb msb lsb left channel right channel sdin aoutl aoutr audio word length (awl) figure 18. right-justified format (dac only) lrck sclk msb lsb sdin hp/line outb lsb left channel right channel msb lsb msb audio word length (awl) 1/fs hp/line outa figure 19. dsp mode format)
ds680a1 37 CS42L52 the device will remain in the power-down state until the reset pin is brought high. the control port is ac- cessible once reset is high and the desired register settings can be loaded per the interface descriptions in the ?register description? on page 42 . once mclk is valid, the quiescent voltage, vq, and the internal voltage referenc e, filt+, will begin power- ing up to normal operation. the charge pump slowly powers up and charges the capacitors. power is then applied to the headphone amplifiers and switched-capacitor filters, and the analog/digital outputs enter a mut- ed state. once lrck is valid, mclk occurrences are counted over one lrck period to determine the mclk/lrck frequency ratio and normal operation begins. 4.9 recommended power-up sequence 1. hold reset low until the power supplies are stable. 2. bring reset high. 3. the default state of the pdn bit is ?1?b. load the de sired register settings wh ile keeping the pdn bit set to ?1?b. 4. start mclk to the appropriat e frequency, as discussed in section 4.6 . 5. set the pdn bit to ?0?b. 6. apply lrck, sclk and sdin for normal operation to begin. 7. bring reset low if the analog or digital supplies drop below the recommended operating condition to prevent power glitch related issues. 4.10 recommended power-down sequence to minimize audible pops when turning off or placing the codec in standby, 1. mute the dac?s and adc?s. 2. set the pdn bit in the power cont rol register to ?1?b. the codec will not power do wn until it reaches a fully muted sate. do not remove mclk until after the par t has fully muted. note that it may be necessary to disable the soft ramp and/or zero cross volume transitions to achieve faster muting/power down. 3. bring reset low.
38 ds680a1 CS42L52 4.11 control port operation the control port is used to access the registers allowing the codec to be configured for the desired oper- ational modes and formats. the operation of the contro l port may be completely asynchronous with respect to the audio sample rates. however, to avoid potential interference problems, the control port pins should remain static if no operation is required. the control port operates using an i2c interf ace with the codec acting as a slave device. 4.11.1 i2c control sda is a bidirectional data line. data is clocked into and out of the part by the clock, scl. the signal tim- ings for a read and write cycle are shown in figure 20 and figure 21 . a start condition is defined as a falling transition of sda while the cl ock is high. a stop condition is de fined as a rising transition of sda while the clock is high. all other transitions of sda occu r while the clock is low. the first byte sent to the CS42L52 after a start condition consists of a 7-bit chip address field and a r/w bit (high for a read, low for a write). the upper 7 bits of the address field are fixed at 1001010. to communicate with the CS42L52, the chip address field, which is the first byte sent to the cs 42l52, should match 1001010. the eighth bit of the address is the r/w bit. if the operation is a write, the next byte is the memory address pointer (map), which selects the register to be read or written. if the operation is a read, the contents of the register point- ed to by the map will be output. sett ing the auto-increment bit in map allows successive reads or writes of consecutive registers. each byte is separated by an acknowledge bit. the ack bit is output from the CS42L52 after each input byte is read and is inpu t to the CS42L52 from the microcontroller after each transmitted byte. since the read operation cannot set the map, an aborte d write operation is used as a preamble. as shown in figure 21 , the write operation is aborted after the acknowledge for the map byte by sending a stop con- dition. the following pseudocode illu strates an aborted wr ite operation followed by a read operation. send start condition. send 10010100 (chip address & write operation). receive acknowledge bit. 4 5 6 7 24 25 scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 0 1 0 0 sda incr 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0 0 1 2 3 8 9 12 16 17 18 19 10 11 13 14 15 27 28 26 data +n figure 20. control port timing, i2c write scl chip address (write) map byte data data +1 start ack stop ack ack ack 1 0 0 1 0 1 0 0 sda 1 0 0 1 0 1 0 1 chip address (read) start incr 6 5 4 3 2 1 0 7 0 7 0 7 0 no 16 8 9 12 13 14 15 4 5 6 7 0 1 20 21 22 23 24 26 27 28 2 3 10 11 17 18 19 25 ack data + n stop figure 21. control port timing, i2c read
ds680a1 39 CS42L52 send map byte, auto-increment off. receive acknowledge bit. send stop condition, aborting write. send start condition. send 10010101 (chip address & read operation). receive acknowledge bit. receive byte, contents of selected register. send acknowledge bit. send stop condition. setting the auto-increment bit in the map allows succes sive reads or writes of consecutive registers. each byte is separated by an acknowledge bit. 4.11.2 memory address pointer (map) the map byte comes after the address byte and selects the register to be read or written. refer to the pseudo code above for implementation details. 4.11.2.1 map increment (incr) the device has map auto-increment c apability enabled by the incr bit (the msb) of the map. if incr is set to 0, map will stay constant for successive i2c writes or reads. if incr is set to 1, map will auto-in- crement after each byte is read or written, allowing block reads or writes of successive registers.
40 ds680a1 CS42L52 5. register qu ick reference ( default values are shown below the bit names ) i2c address : 1001010[r/w ] - 10010100 = 0x94(write); 10010101 = 0x95(read) adr. function 7 6 5 4 3 2 1 0 01h id chipid4 chipid3 chipid2 chipid1 chipid0 revid2 revid1 revid0 p42 111 00xx x 02h power ctl 1 pdn_chrg reserved reserved pdn_pgab pdn_pgaa pdn_adcb pdn_adca pdn p42 000 00001 03h power ctl 2 reserved reserved reserved ovrdb ovrda pdn_micb pdn_mica pdn_bias p43 000 00111 04h power ctl 3 pdn_hpb1 pdn_hpb0 pdn_hpa1 pdn_hpa0 pdn_spkb1 pdn_spkb0 pdn_spka1 pdn_spka0 p44 000 00101 05h clocking ctl auto speed1 speed0 32kgroup videoclk ratio1 ratio0 mclkdiv2 p44 101 00000 06h interface ctl 1 m/s inv_sclk adcdif dsp dacdif1 dacdif0 awl1 awl0 p46 000 00000 07h interface ctl 2 reserved sclk=mclk digloop 3st_sp inv_swch biaslvl2 biaslvl1 biaslvl0 p47 000 00000 08h input a select adcasel2 adcasel1 adcasel0 p gaasel5 pgaasel4 pgaasel3 pgaasel2 pgaasel1 p48 100 00001 09h input b select adcbsel2 adcbsel1 adcbsel0 p gabsel5 pgabsel4 pgabsel3 pgabsel2 pgabsel1 p48 100 00001 0ah analog, hpf ctl hpfb hpfrzb hpfa hpfrza anlgsftb anlgzcb anlgsfta anlgzca p49 101 00101 0bh adc hpf cor- ner freq. reserved reserved reserved reserved hpfb_cf1 hpfb_cf0 hpfa_cf1 hpfa_cf0 p50 000 00000 0ch misc. adc ctl adcb=a digmix digsum1 digsum0 inv_adcb inv_adca adcbmute adcamute p50 000 00000 0dh playback ctl 1 hpgain2 hpgain1 hpgain0 pl ybckb=a inv_pcmb inv_pcma mstbmute mstamute p51 011 00000 0eh misc. ctl passthrub passthrua passbmute passamute freeze deemph digsft digzc p52 000 00010 0fh playback ctl 2 hpbmute hpamute spkbmute spkamute spkb=a spkswap spkmono mute50/50 p53 000 00 00 10h mica amp ctl reserved micasel micacfg micag ain4 micagain3 micagain2 micagain1 micagain0 p54 000 00000 11h micb amp ctl reserved micbsel micbcfg micbg ain4 micbgain3 micbgain2 micbgain1 micbgain0 p54 000 00000 12h pgaa vol, misc alcasrdis alcazcdis pgaavol5 pgaavol4 pgaavol3 pgaavol2 pgaavol1 pgaavol0 p55 000 00000 13h pgab vol, misc alcbsrdis alcbzcdis pgabvol5 pgabvol4 pgabvol3 pgabvol2 pgabvol1 pgabvol0 p55 000 00000 14h passthru a vol passavol7 passavol6 passavol5 passavol4 passavol3 passavol2 passavol1 passavol0 p56 000 00000 15h passthru b vol passbvol7 passbvol6 passbvol5 passbvol4 passbvol3 passbvol2 passbvol1 passbvol0 p56 000 00000 16h adca vol adcavol7 adcavol6 adcavol5 adcavol4 adcavol3 adcavol2 adcavol1 adcavol0 p57 000 00000 17h adcb vol adcbvol7 adcbvol6 adcbvol5 adc bvol4 adcbvol3 adcbvol2 adcbvol1 adcbvol0 p57 000 00000 18h adcmixa vol amixamute amixavol6 amixavol5 amixavol4 amixavol3 amixavol2 amixavol1 amixavol0 p58 100 00000 19h adcmixb vol amixbmute amixbvol6 amixbvol5 amixbvol4 amixbvol3 amixbvol2 amixbvol1 amixbvol0 p58 100 00000 1ah pcmmixa vol pmixamute pmixavol6 pmixavol5 pmixavol4 pmixavol3 pmixavol2 pmixavol1 pmixavol0 p58 000 00000
ds680a1 41 CS42L52 1bh pcmmixb vol pmixbmute pmixbvol6 pmixbvol5 pmixbvol4 pmixbvol3 pmixbvol2 pmixbvol1 pmixbvol0 p58 0 0 0 0 000 0 1ch beep freq, on time freq3 freq2 freq1 freq0 ontime3 ontime2 ontime1 ontime0 p59 0 0 0 0 000 0 1dh beep vol, off time offtime2 offtime1 offtime0 bpvol4 bpvol3 bpvol2 bpvol1 bpvol0 p60 0 0 0 0 000 0 1eh beep, tone cfg. beep1 beep0 beepmixdis treb_cf1 treb_cf0 bass_cf1 bass_cf0 tc_en p61 0 0 0 0 000 0 1fh tone ctl treb3 treb2 treb1 treb0 bass3 bass2 bass1 bass0 p62 1 0 0 0 100 0 20h master a vol mstavol7 mstavol6 mstavol5 mstavol4 mstavol3 mstavol2 mstavol1 mstavol0 p63 0 0 0 0 000 0 21h master b vol mstbvol7 mstbvol6 mstbvol5 ms tbvol4 mstbvol3 mstbvol2 mstbvol1 mstbvol0 p63 0 0 0 0 000 0 22h headphone a volume hpavol7 hpavol6 hpavol5 hpavol4 hpavol3 hpavol2 hpavol1 hpavol0 p63 0 0 0 0 000 0 23h headphone b volume hpbvol7 hpbvol6 hpbvol5 hpbvol4 hpbvol3 hpbvol2 hpbvol1 hpbvol0 p63 0 0 0 0 000 0 24h speaker a volume spkavol7 spkavol6 spkavol5 spkavol4 spkavol3 spkavol2 spkavol1 spkavol0 p64 0 0 0 0 000 0 25h speaker b volume spkbvol7 spkbvol6 spkbvol5 spkbvol4 spkbvol3 spkbvol2 spkbvol1 spkbvol0 p64 0 0 0 0 000 0 26h channel mixer & swap pcmaswp1 pcmaswp0 pcmbswp1 pcmbswp0 adcaswp1 adcaswp0 adcbswp1 adcbswp0 p64 0 0 0 0 000 0 27h limit ctl 1, thresholds lmax2 lmax1 lmax0 cush2 cush1 cush0 limsrdis limzcdis p65 0 0 0 0 000 0 28h limit ctl 2, release rate limit limit_all limrrate5 limrrate4 limrrate3 limrrate2 limrrate1 limrrate0 p66 0 1 1 1 111 1 29h limiter attack rate reserved reserved limarate5 limarate4 limarate3 limarate2 limarate1 limarate0 p67 1 1 0 0 000 0 2ah alc ctl 1, attack rate alcb alca alcarate5 aalcrate4 alcarate3 alcarate2 alcarate1 alcarate0 p67 0 0 0 0 000 0 2bh alc release rate reserved reserved alcrrate5 alcrrate4 alcrrate3 alcrrate2 alcrrate1 alcrrate0 p68 0 0 1 1 111 1 2ch alc thresh- olds alcmax2 alcmax1 alcmax0 alcmin2 alcmin1 alcmin0 reserved reserved p68 0 0 0 0 000 0 2dh noise gate ctl ngall ng ngboost thresh2 thresh1 thresh0 ngdelay1 ngdelay0 p69 0 0 0 0 000 0 2eh overflow & clock status reserved spclkerr dspbovfl dspaovfl pcmaovfl pcmbovfl adcaovfl adcbovfl p70 0 0 0 0 000 0 2fh battery com- pensation battcmp vpmonitor reserved rese rved vpref3 vpref2 vpref1 vpref0 p71 0 0 0 0 000 0 30h vp battery level vplvl7 vplvl6 vplvl5 vplvl4 vplvl3 vplvl2 vplvl1 vplvl0 p72 0 0 0 0 000 0 31h speaker status reserved reserved spkashrt spkbshrt spkr/hp reserved twrn terr p72 0 0 0 0 000 0 32h temperature monitor control release reserved reserved reserved reserved reserved reserved reserved p73 0 0 1 1 101 1 33h thermal fold- back reserved reserved reserved reserv ed thrfld spkattn2 spkattn1 spkattn0 p73 0 0 0 0 000 0 34h charge pump frequency chgfreq3 chgfreq2 chgfreq1 chgfreq0 reserved reserved reserved reserved p74 0 1 0 1 111 1 i2c address : 1001010[r/w ] - 10010100 = 0x94(write); 10010101 = 0x95(read) adr. function 7 6 5 4 3 2 1 0
42 ds680a1 CS42L52 6. register description all registers are read/write except for the chip i.d. and revision register and interrupt status register which are read only. see the following bit definition tables for bit assignment information. the default state of each bit after a power-up sequence or reset is listed in each bit descriptio n. all ?reserved? bits must maintain their default value. 6.1 chip i.d. and revisi on register (address 01h) (read only) 6.1.1 chip i.d. (read only) i.d. code for the CS42L52. 6.1.2 chip revision (read only) CS42L52 revision level. 6.2 power control 1 (address 02h) 6.2.1 power down adc charge pump configures the power state of the adc charge pump. 6.2.2 power down pgax configures the power state of pga channel x. notes: 1. the CS42L52 employs a clever scheme for controlling the po wer to the pga when passthru ( ?passthru analog? on page 52 ) is enabled. refer to the referenced application for more information. 2. this bit is also used in conjunction with ainx_sel bi ts to determine the analog input path to the adc. refer to ?adc input select? on page 48 for the required settings. 76543210 chipid4 chipid3 chipi d2 chipid1 chipid0 revid2 revid1 revid0 chipid[4:0] device 11100 CS42L52 revid[2:0] revision level 000 a0 001 a1 010 b0 76543210 pdn_chrg reserved reserved pdn_pgab pdn_pgaa pdn_adcb pdn_adca pdn pdn_chrg adc charge pump status 0 powered up 1 powered down pdn_pgax pga status 0 powered up (only when the adc or the analog passthru is used) 1 powered down application ?analog in to analog out passthru? on page 32
ds680a1 43 CS42L52 6.2.3 power down adcx configures the power state of adc channel x. notes: 1. the CS42L52 employs a clever scheme for controlling the pow er to the adc when passthru ( ?passthru analog? on page 52 ) and pdn_ovrd ( ?power down adc override? on page 43 ) are enabled. refer to the referenced application. 6.2.4 power down configures the power stat e of the entire codec. 6.3 power control 2 (address 03h) 6.3.1 power down adc override configures an override of the power down control for adcx. 6.3.2 power down micx configures the power state of the mi crophone pre-amplifier for channel x. 6.3.3 power down mic bias configures the power state of the microphone bias circuit. pdn_adcx adc status 0 powered up 1 powered down application ?analog in to analog out passthru? on page 32 pdn codec status 0 powered up 1 powered down 76543210 reserved reserved reserved ovrdb o vrda pdn_micb pdn_mica pdn_bias ovrdx pdn_adc override 0 disable 1 enable application ?analog in to analog out passthru? on page 32 pdn_micx mic pre-amp status 0 powered up 1 powered down application ?mic inputs? on page 27 pdn_bias mic bias status 0 powered up 1 powered down
44 ds680a1 CS42L52 6.4 power control 3 (address 04h) 6.4.1 headphone power control configures how the spk/hp_sw pin, 6, controls the power for the headphone am plifier. 6.4.2 speaker power control configures how the spk/hp_sw pin, 6, controls the power for the speaker amplifier. 6.5 clocking control (address 05h) 6.5.1 auto-detect configures the auto-detect circuitry for detecting the speed mode of the codec when operating as a slave. notes: 1. the speed[1:0] bits are igno red and speed is de termined by the mclk/lrck ratio. 2. when auto is disabled and the codec operates in master mode, the mclkdiv2 bit is ignored. 3. certain sample and mclk fre quencies require setting the speed [1:0] bits, the 32k_group bit ( ?32khz sample rate group? on page 45 ) and/or the videoclk bit ( ?27 mhz video clock? on page 45 ) and ratio[1:0] bits ( ?internal mclk/lrck ratio? on page 45 ). low sample rates may also affect dynamic range performance in the typical aud io band. refer to the referenced application for more information. 76543210 pdn_hpb1 pdn_hpb0 pdn_hpa1 pdn_hp a0 pdn_spkb1 pdn_spkb0 pdn_spka1 pdn_spka0 pdn_hpx[1:0] headphone status 00 headphone channel is on when the spk/hp_sw pin, 6, is lo. headphone channel is off when the spk/hp_sw pin, 6, is hi. 01 headphone channel is on when the spk/hp_sw pin, 6, is hi. headphone channel is off when the spk/hp_sw pin, 6, is lo. 10 headphone channel is always on. 11 headphone channel is always off. pdn_spkx[1:0] speaker status 00 speaker channel is on when the spk/hp_sw pin, 6, is lo. speaker channel is off when the spk/hp_sw pin, 6, is hi. 01 speaker channel is on when the spk/hp_sw pin, 6, is hi. speaker channel is off when the spk/hp_sw pin, 6, is lo. 10 speaker channel is always on. 11 speaker channel is always off. 76543210 auto speed1 speed0 32k_group videoclk ratio1 ratio0 mclkdiv2 auto auto-detection of speed mode 0 disabled 1 enabled application: ?serial port clocking? on page 34
ds680a1 45 CS42L52 6.5.2 speed mode configures the speed mode of the codec in slave mode and sets the appropriate mclk divide ratio for lrck and sclk in master mode. notes: 1. slave/master mode is determined by the m/s bit in ?master/slave mode? on page 46 . 2. certain sample and mclk freq uencies require setting the speed [1:0] bits, the 32k_group bit ( ?32khz sample rate group? on page 45 ) and/or the videoclk bit ( ?27 mhz video clock? on page 45 ) and ratio[1:0] bits ( ?internal mclk/lrck ratio? on page 45 ). low sample rates may also affect dynamic range performance in the typical a udio band. refer to the referenced application for more information. 3. these bits are ignored when the auto bit ( ?auto-detect? on page 44 ) is enabled. 6.5.3 32khz sample rate group specifies whether or not the input/output sa mple rate is 8 khz, 16 khz or 32 khz. 6.5.4 27 mhz video clock specifies whether or not the exte rnal mclk frequency is 27 mhz 6.5.5 internal mclk/lrck ratio configures the internal mclk/lrck ratio. speed[1:0] slave mode master mode serial port speed mclk/lrck ratio sclk/lrck ratio 00 double-speed mode (dsm - 50 khz -100 khz fs) 512 64 01 single-speed mode (ssm - 4 khz -50 khz fs) 256 64 10 half-speed mode (hsm - 12.5khz -25 khz fs) 128 64 11 quarter-speed mode (qsm - 4 khz -12.5 khz fs) 128 64 application: ?serial port clocking? on page 34 32kgroup 8 khz, 16 khz or 32 khz sample rate? 0 no 1yes application: ?serial port clocking? on page 34 videoclk 27 mhz mclk? 0 no 1yes application: ?serial port clocking? on page 34 ratio[1:0] internal mclk cycles per lrck sclk/lrck ratio in master mode 00 128 64 01 125 62 10 132 66 11 136 68 application: ?serial port clocking? on page 34
46 ds680a1 CS42L52 6.5.6 mclk divide by 2 divides the input mclk by 2 pr ior to all internal circuitry. note: in slave mode, this bit is ignored when the auto bit ( ?auto-detect? on page 44 ) is disabled. 6.6 interface control 1 (address 06h) 6.6.1 master/slave mode configures the serial port i/o clocking. 6.6.2 sclk polarity configures the polarity of the sclk signal. 6.6.3 adc interface format configures the digital interf ace format for data on sdout. 6.6.4 dsp mode configures a data-packed interface format for both the adc and dac. notes: 1. select the audio word length using the awl[1:0] bits ( ?audio word length? on page 47 ). 2. the interface format for both the adc and the da c must be set to ?left-justified? when dsp mode is enabled. mclkdiv2 mclk signal into codec 0 no divide 1 divided by 2 application: ?serial port clocking? on page 34 76543210 m/s inv_sclk adcdif dsp dacdif1 dacdif0 awl1 awl0 m/s serial port clocks 0 slave (input only) 1 master (output only) inv_sclk sclk polarity 0 not inverted 1 inverted adcdif adc interface format 0 left justified 1i2s application: ?digital interface formats? on page 36 dsp dsp mode 0 disabled 1 enabled application: ?dsp mode? on page 36
ds680a1 47 CS42L52 6.6.5 dac interface format configures the digital interf ace format for data on sdin. note: select the audio word leng th for right justified using the awl[1:0] bits ( ?audio word length? on page 47 ). 6.6.6 audio word length configures the audio sample word length used for the data into sdin and out of sdout. note: when the internal mclk/lrck ratio is set to 125 in master mode, the 32-bit data width option for dsp mode is not valid unless sclk=mclk. 6.7 interface contro l 2 (address 07h) 6.7.1 sclk equals mclk configures the sclk signal source for master mode. note: this bit is only valid for mclk = 12.0000 mhz. 6.7.2 sdout to sdin digital loopback configures an internal loops the signal on the sdout pin to sdin. dacdif[1:0] dac interface format 00 left justified, up to 24-bit data 01 i2s, up to 24-bit data 10 right justified 11 reserved application: ?digital interface formats? on page 36 awl[1:0] audio word length dsp mode right justified (dac only) 00 32-bit data 24-bit data 01 24-bit data 20-bit data 10 20-bit data 18-bit data 11 16-bit data 16-bit data application: ?dsp mode? on page 36 76543 2 1 0 reserved sclk=mclk digloop 3st_sp in v_swch biaslvl2 biaslvl1 biaslvl0 sclk=mclk output sclk 0 re-timed signal, synchronously derived from mclk 1 non-retimed, mclk signal digloop internal loopback 0 disabled; sdout internally disconnected from sdin 1 enabled; sdout internally connected to sdin
48 ds680a1 CS42L52 6.7.3 tri-state serial port interface determines the state of the serial port drivers. notes: 1. slave/master mode is determined by the m/s bit in ?master/slave mode? on page 46 . 2. when the serial port is tri-stated in master mode , the adc and dac serial ports are clocked internally. 6.7.4 speaker/headphone switch invert determines the control signal po larity of the spk/hp_sw pin. 6.7.5 mic bias level sets the output voltage level on the micbias output pin. 6.8 input x select: adca and pgaa (address 08h), ad cb and pgab (address 09h) 6.8.1 adc input select selects the specified analog input signal into adcx. 3st_sp serial port status slave mode master mode 0 serial port clocks are inputs and sdout is output serial port clocks and sdout are outputs 1 serial port clocks are inputs and sdout is hi-z serial port clocks and sdout are hi-z inv_swch spk/hp_sw pin 6 control 0 not inverted 1 inverted biaslvl[2:0] output bias level 000 0.5 x va 001 0.6 x va 010 0.7 x va 011 0.8 x va 100 0.83 x va 101 0.91 x va 110 reserved 111 reserved 7 6 5 4 3210 adcasel2 adcasel1 adcasel0 pgaasel5 p gaasel4 pgaasel3 pgaasel2 pgaasel1 adcxsel[2:0] selected input to adcx 000 ain1x 001 ain2x 010 ain3x 011 ain4x 100 pgax - use pgaxsel bits ( ?pga input mapping? on page 49 ) to select input channels 101 reserved 110 reserved 111 reserved application: ?analog inputs? on page 26
ds680a1 49 CS42L52 6.8.2 pga input mapping selects one or sums/mixes the analog input signal into the pga. each bit of the pgax_sel[5:1] word corresponds to individual channels (i.e. pgax_sel 1 selects ain1x, pgax_sel2 selects ain2x, etc.). 6.9 analog & hpf control (address 0ah) 6.9.1 adcx high-pass filter configures the internal high-pass filter after adcx. 6.9.2 adcx high-pass filter freeze configures the high pass filter?s digital dc subtraction and/or calibration after adcx. 6.9.3 ch. x analog soft ramp configures an incremental volume ramp from the current level to the new level at the specified rate. 6.9.4 ch. x analog zero cross configures when the signal level changes occur for the analog volume controls. note: if the signal does not encounter a zero crossing, the requested volume change will occur after a timeout period of 1024 sample periods (app roximately 10.7 ms at 48 khz sample rate). pgaxsel[5:1] selected input to pgax (examples) 00000 no inputs selected 00001 ain1x 00010 ain2x 00100 ain3x 01000 ain4x 10000 micx; for single-ended mic inputs, use micxsel ( ?mic x select? on page 54 ) to select mic 1 or mic 2; for differential mic inputs, enable micxcfg ( ?micx configuration? on page 55 ) 10001 micx + ain1x 10011 micx + ain1x + ain2x application: ?analog inputs? on page 26 note: table does not show all possible combinations. 76543210 hpfb hpfrzb hpfa hpfrza anlgsftb anlgzcb anlgsfta anlgzca hpfx high pass filter status 0 disabled 1 enabled hpfrzx high pass filter digital subtraction 0 continuous dc subtraction 1 frozen dc subtraction anlgsftx volume changes affected analog volume controls 0 do not occur with a soft ramp micxgain[4:0] ( ?micx gain? on page 55 ), pgaxvol[5:0] ( ?pgax volume? on page 56 ), and passxvol[7:0] ( ?passthru x volume? on page 56 ) 1 occur with a soft ramp ramp rate: 1/2 db every 16 lrck cycles anlgzcx volume changes affected analog volume controls 0 do not occur on a zero cross- ing micxgain[4:0] ( ?micx gain? on page 55 ), pgaxvol[5:0] ( ?pgax volume? on page 56 ), and passxvol[7:0] ( ?passthru x volume? on page 56 ) 1 occur on a zero crossing
50 ds680a1 CS42L52 6.10 adc hpf corner frequency (address 0bh) 6.10.1 hpf x corner frequency sets the corner frequency (-3 db point) fo r the internal high-pass filter (hpf). 6.11 misc. adc cont rol (address 0ch) 6.11.1 adc channel b=a configures independent or ganged control of the mic, pga, passthr u, adc and the alc. 6.11.2 digital mux selects the signal source for the adc serial port 6.11.3 digital sum configures a mix/swap of adca and adcb. 6.11.4 invert adc signal polarity configures the polarity of the adc signal. 76543210 reserved reserved reserved reserved hpfb_cf1 hpfb_cf0 hpfa_cf1 hpfa_cf0 hpfx_cf[1:0] hpf corner frequency setting (fs=48 khz) 00 normal setting as specified in ?adc digital filter characteristics? on page 14 01 119 hz 10 236 hz 11 464 hz 76543210 adcb=a digmux digsum1 digsum0 inv_ adcb inv_adca adcbmute adcamute adcb=a single volume control 0 disabled 1 enabled digmux sdout signal source 0 adc 1dsp digsum[1:0] serial output signal left channel right channel 00 adca adcb 01 (adca + adcb)/2 (adca + adcb)/2 10 (adca - adcb)/2 (adca - adcb)/2 11 adcb adca inv_adcx adc signal polarity 0 not inverted 1 inverted
ds680a1 51 CS42L52 6.11.5 adc mute configures a digital mute on adc channel x. 6.12 playback control 1 (address 0dh) 6.12.1 headphone analog gain selects the gain multiplier for the headphone/line outputs. note: refer to ?line output voltage level characteristics? on page 18 and ?headphone output power characteristics? on page 19 . 6.12.2 playback volume setting b=a configures independent or ganged volume control of all playback channels. 6.12.3 invert pcm signal polarity configures the polarity of the digital input signal. 6.12.4 master playback mute configures a digital mute on the master volume control for channel x. note: the muting function is affected by the digsft ( ?digital soft ramp? on page 53 ) and digzc ( ?digital zero cross? on page 53 ) bits. adcxmute adc mute 0 not inverted 1 inverted 76543210 hpgain2 hpgain1 hpgain0 plybckb=a inv_pcmb inv_pcma mstbmute mstamute hpgain[2:0] headphone/line gain setting (g) 000 0.3959 001 0.4571 010 0.5111 011 0.6047 100 0.7099 101 0.8399 110 1.000 111 1.1430 plybckb=a single volume control for all playback channels 0 disabled 1 enabled inv_pcmx pcm signal polarity 0 not inverted 1 inverted mstxmute master mute 0 not inverted 1 inverted
52 ds680a1 CS42L52 6.13 miscellaneous controls (address 0eh) 6.13.1 passthru analog configures an analog passthru from the pga inputs to the headphone/line outputs. notes: 1. the passthru volume control is realized using a combination of the pga volume control settings ( ?pgax volume? on page 56 ) and the headphone amplifier volume control settings (hidden). when passthru is enabled and the pga to adc path is selected, the sign al seen by the adc will change depending on the passthru volume setting. 6.13.2 passthru mute configures an analog mute on the channel x analog in to analog out passthru. 6.13.3 freeze registers configures a hold on all register settings. 6.13.4 hp/speaker de-emphasis configures a 15 s/50 s digital de-emphasis filter response on the headphone/line and speaker outputs . 76543210 passthrub passthrua passbmute passamute freeze deemph digsft digzc passthrux analog in routed to hp/line output 0 disabled 1 enabled passxmute passthru mute 0 disabled 1 enabled freeze control port status 0 register changes take effect immediately 1 modifications may be made to all control port register s without the changes taking effect until after the freeze is disabled. deemphasis control port status 0 disabled 1 enabled
ds680a1 53 CS42L52 6.13.5 digital soft ramp configures an incremental volume ramp from the current level to the new level at the specified rate. 6.13.6 digital zero cross configures when the signal level changes occur for the digital volume controls. notes: 1. if the signal does not encounter a zero crossing , the requested volume change will occur after a timeout period between 1024 and 2048 sample periods (21.3 ms to 42.7 ms at 48 khz sample rate). 2. the zero cross function is independently monitored and implemented for each channel. 3. the dis_limsft bit ( ?limiter soft ramp disable? on page 65 ) is ignored when zero cross is enabled. 6.14 playback control 2 (address 0fh) 6.14.1 headphone mute configures a digital mute on headphone channel x. 6.14.2 speaker mute configures a digital mute on speaker channel x. digsft volume changes affected digital volume controls 0 do not occur on a zero cross- ing mstxmute ( ?master playback mute? on page 51 ), hpxmute, spkxmute ( ?playback control 2 (address 0fh)? on page 53 ), adcxvol[7:0] ( ?adcx volume? on page 57 ), amixxmute, amixxvol[7:0] ( ?adc mixer channel x volume? on page 58 ), pmixxmute, pmixxvol[7:0] ( ?pcm mixer channel x volume? on page 58 ), mstxvol[7:0] ( ?master volume control? on page 63 ), hpxvol[7:0] ( ?headphone volume control? on page 63 ), spkxvol[7:0] ( ?speaker volume control? on page 64 ), alc and limiter attack/release ( page 66 to page 68 ) 1 occur on a zero crossing ramp rate: 1/8 db every lrck cycle digzc volume changes affected digital volume controls 0 do not occur on a zero cross- ing mstxmute ( ?master playback mute? on page 51 ), hpxmute, spkxmute ( ?playback control 2 (address 0fh)? on page 53 ), adcxvol[7:0] ( ?adcx volume? on page 57 ), amixxmute, amixxvol[7:0] ( ?adc mixer channel x volume? on page 58 ), pmixxmute, pmixxvol[7:0] ( ?pcm mixer channel x volume? on page 58 ), mstxvol[7:0] ( ?master volume control? on page 63 ), hpxvol[7:0] ( ?headphone volume control? on page 63 ), spkxvol[7:0] ( ?speaker volume control? on page 64 ), alc and limiter attack/release ( page 66 to page 68 ) 1 occur on a zero crossing 76543210 hpbmute hpamute spkbmute spkamut e spkb=a spkswap spkmono mute50/50 hpxmute headphone mute 0 disabled 1 enabled spkxmute speaker mute 0 disabled 1 enabled
54 ds680a1 CS42L52 6.14.3 speaker volume setting b=a configures independent or ganged volume control of the speaker volume and mute. 6.14.4 speaker channel swap configures a channel swap on the speaker channels. 6.14.5 speaker mono control configures a parallel full bridge output for the speaker channels. 6.14.6 speaker mute 50/50 control configures how the speaker channels mute. 6.15 micx amp control: mic a (address 10h) & mic b (address 11h) 6.15.1 mic x select selects one of two single-ended mic inputs on channel x. spkb=a single volume control for the speaker channel 0 disabled 1 enabled spkswap speaker output 0 channel a 1 channel b application: ?mono speaker output configuration? on page 33 spkmono parallel full bridge output 0 disabled 1 enabled application: ?mono speaker output configuration? on page 33 mute50/50 speaker mute 50/50 0 disabled; the pwm amplifiers outputs modulated silence when spkxmute is enabled. 1 enabled; the pwm amplifiers switch at an exact 50%- duty-cycle signal (not mo dulated) when spkxmute is enabled. 7 6543210 reserved micxsel micxcfg micxgain4 micx gain3 micxgain2 micxgain1 micxgain0 micxsel mic x selection 0 mic 1x 1 mic 2x application: ?mic inputs? on page 27
ds680a1 55 CS42L52 6.15.2 micx configuration configures the input topology for micx. 6.15.3 micx gain sets the gain of the microphone pre-amplifier. 6.16 pgax vol. & alcx transition ctl.: alc, pga a (address 12h) & alc, pga b (address 13h) 6.16.1 alcx soft ramp disable configures an override of the analog soft ramp setting. 6.16.2 alcx zero cross disable configures an override of the analog zero cross setting. micxcfg mic input topology 0 single-ended 1 differential application: ?mic inputs? on page 27 micxgain[4:0] gain 11111 32 db ... ... 10000 32 db ... ... 00000 16 db step size: 1 db application: ?mic inputs? on page 27 7 6543210 alcxsrdis alcxzcdis pgaxvol5 pgaxvol4 pgaxvol3 pgaxvol2 pgaxvol1 pgaxvol0 alcxsrdis alc soft ramp disable 0 off; alc attack rate is dictated by the anlgsft ( ?ch. x analog soft ramp? on page 49 ) setting 1 on; alc volume changes take effect in one step, regardless of the anlgsft setting. application: ?automatic level control (alc)? on page 27 alcxzcdis alc zero cross disable 0 off; alc attack rate is dictated by the anlgzc ( ?ch. x analog zero cross? on page 49 ) setting 1 on; alc volume changes take effect at any time, regardless of the anlgzc setting. application: ?automatic level control (alc)? on page 27
56 ds680a1 CS42L52 6.16.3 pgax volume sets the volume/gain of the programmable gain amplifier (pga). note: the pgaxvol bits are ignor ed when the passthrux bit ( ?passthru analog? on page 52 ) is en- abled. 6.17 passthru x volume: pa ssavol (address 14h) & pass bvol (address 15h) 6.17.1 passthru x volume sets the volume/gain of the signal routed from the pga to the headphone/line output. notes: 1. this register is igno red when the passthrux bit ( ?passthru analog? on page 52 ) is disabled. 2. the step size may deviate from 0.5 db at settings below -40 db. code settings 0x95, 0xa1, 0xad and 0xb9 are not guaranteed to be monotonic. pgaxvol[5:0] volume 01 1111 12 db ... ... 01 1000 12 db ... ... 00 0001 +0.5 db 00 0000 0 db 11 1111 -0.5 db ... ... 10 1000 -6.0 db ... ... 10 0000 -6.0 db step size: 0.5 db 76543210 passxvol7 passxvol6 passxvol5 passxvol4 passxvol3 passxvol2 passxvol1 passxvol0 passxvol[7:0] gain 0111 1111 12 db ... ... 0001 1000 12 db ... ... 0000 0001 +0.5 db 0000 0000 0 db 11111 1111 -0.5 db ... ... 1000 1000 -60.0 db ... ... 1000 0000 -60.0 db step size: 0.5 db (approximate) application: ?analog in to analog out passthru? on page 32
ds680a1 57 CS42L52 6.18 adcx volume control: adcavol (address 16h) & adcbv ol (address 17h) 6.18.1 adcx volume sets the volume of the adc signal out the serial data output (sdout). 76543210 adcavol7 adcavol6 adcavol5 adcavol4 adcavol3 adcavol2 adcavol1 adcavol0 adcxvol[7:0] volume 0111 1111 24 db ... ... 0001 1000 24 db ... ... 0000 0000 0 db 1111 1111 -1.0 db 1111 1110 -2.0 db ... ... 1010 0000 -96.0 db ... ... 1000 0000 -96.0 db step size: 1.0 db
58 ds680a1 CS42L52 6.19 adcx mixer volume: adca (address 18h) & adcb (address 19h) 6.19.1 adc mixer channel x mute configures a digital mute on the adc mix in the dsp. 6.19.2 adc mixer channel x volume sets the volume/gain of the adc mix in the dsp. 6.20 pcmx mixer volume: pcma (address 1ah) & pcmb (address 1bh) 6.20.1 pcm mixer channel x mute configures a digital mute on the pcm mix from the serial data input (sdin) to the dsp. 6.20.2 pcm mixer channel x volume sets the volume/gain of the pcm mix from t he serial data input (sdin) to the dsp. 7 6543210 amixxmute amixxvol6 amixxvol5 amixxvol4 amixxvol3 amixxvol2 amixxvol1 amixxvol0 amixxmute adc mixer mute 0 disabled 1 enabled amixxvol[6:0] volume 001 1000 +12.0 db ... ... 000 0001 +0.5 db 000 0000 0 db 111 1111 -0.5 db ... ... 001 1001 -51.5 db step size: 0.5 db 7 6543210 pmixxmute pmixxvol6 pmixxvol5 pmixxvol4 pmixxvol3 pmixxvol2 pmixxvol1 pmixxvol0 pmixxmute pcm mixer mute 0 disabled 1 enabled pmixxvol[6:0] volume 001 1000 +12.0 db ... ... 000 0001 +0.5 db 000 0000 0 db 111 1111 -0.5 db ... ... 001 1001 -51.5 db step size: 0.5 db
ds680a1 59 CS42L52 6.21 beep frequency & on time (address 1ch) 6.21.1 beep frequency sets the frequency of the beep signal. notes: 1. this setting must not ch ange when beep is enabled. 2. beep frequency will scale directly wi th sample rate, fs, but is fix ed at the nominal fs within each speed mode. 76543210 freq3 freq2 freq1 freq0 onti me3 ontime2 ontime1 ontime0 freq[3:0] frequency (fs = 12, 24, 48 or 96 khz) pitch 0000 260.87 hz c4 0001 521.74 hz c5 0010 585.37 hz d5 0011 666.67 hz e5 0100 705.88 hz f5 0101 774.19 hz g5 0110 888.89 hz a5 0111 1000.00 hz b5 1000 1043.48 hz c6 1001 1200.00 hz d6 1010 1333.33 hz e6 1011 1411.76 hz f6 1100 1600.00 hz g6 1101 1714.29 hz a6 1110 2000.00 hz b6 1111 2181.82 hz c7 application: ?beep generator? on page 30
60 ds680a1 CS42L52 6.21.2 beep on time sets the on duration of the beep signal. notes: 1. this setting must not change when beep is enabled. 2. beep on time will scale inversely with sample rate, fs , but is fixed at the nominal fs within each speed mode. 6.22 beep volume & of f time (address 1dh) 6.22.1 beep off time sets the off duration of the beep signal. notes: 1. this setting must not change when beep is enabled. 2. beep off time will scale inversely with sample rate, fs, but is fixed at the nominal fs within each speed mode. ontime[3:0] on time (fs = 12, 24, 48 or 96 khz) 0000 ~86 ms 0001 ~430 ms 0010 ~780 ms 0011 ~1.20 s 0100 ~1.50 s 0101 ~1.80 s 0110 ~2.20 s 0111 ~2.50 s 1000 ~2.80 s 1001 ~3.20 s 1010 ~3.50 s 1011 ~3.80 s 1100 ~4.20 s 1101 ~4.50 s 1110 ~4.80 s 1111 ~5.20 s application: ?beep generator? on page 30 76543210 offtime2 offtime1 offtime0 bpvol4 bpvol3 bpvol2 bpvol1 bpvol0 offtime[2:0] off time (fs = 48 or 96 khz) 000 ~1.23 s 001 ~2.58 s 010 ~3.90 s 011 ~5.20 s 100 ~6.60 s 101 ~8.05 s 110 ~9.35 s 111 ~10.80 s application: ?beep generator? on page 30
ds680a1 61 CS42L52 6.22.2 beep volume sets the volume of the beep signal. note: this setting must not ch ange when beep is enabled. 6.23 beep & tone configuration (address 1eh) 6.23.1 beep configuration configures a beep mixed with the hp/line and spk output. notes: 1. when used in analog pass through mode, the output alternates between the si gnal from the pga and the beep signal. the beep signal does not mix with the analog signal from the pga. 2. re-engaging the beep befor e it has completed its initial cycle w ill cause the beep signal to remain on for the maximum ontime duration. 6.23.2 beep mix disable configures how the beep mixes with the serial data input. note: this setting must not ch ange when beep is enabled. beepvol[4:0] gain 00110 +12.0 db 00000 0 db 11111 -2 db 11110 -4 db 00111 -50 db step size: 2 db application: ?beep generator? on page 30 76543210 beep1 beep0 beepmixdis trebcf1 trebcf0 basscf1 basscf0 tcen beep[1:0] beep occurrence 00 off 01 single 10 multiple 11 continuous application: ?beep generator? on page 30 beepmixdis beep output to hp/line and speaker 0 mix enabled; the beep signal mixes with the digital signal from the serial data input. 1 mix disabled; the output alternates between the signal from the serial data input and the beep signal. the beep signal does not mix with the digita l signal from the serial data input. application: ?beep generator? on page 30
62 ds680a1 CS42L52 6.23.3 treble corner frequency sets the corner frequency (-3 db point) for the treble shelving filter. 6.23.4 bass corner frequency sets the corner frequency (-3 db point) for the bass shelving filter. 6.23.5 tone control enable configures the treble and bass activation. 6.24 tone contro l (address 1fh) 6.24.1 treble gain sets the gain of the treble shelving filter. trebcf[1:0] treble corner frequency setting 00 5 khz 01 7 khz 10 10 khz 11 15 khz basscf[1:0] bass corner frequency setting 00 50 hz 01 100 hz 10 200 hz 11 250 hz tcen bass and treble control 0 disabled 1 enabled application: ?beep generator? on page 30 76543210 treb3 treb2 treb1 treb0 bass3 bass2 bass1 bass0 treb[3:0] gain setting 0000 +12.0 db 0111 +1.5 db 1000 0 db 1001 -1.5 db 1111 -10.5 db step size: 1.5 db
ds680a1 63 CS42L52 6.24.2 bass gain sets the gain of the bass shelving filter. 6.25 master volume control: ms ta (address 20h) & mstb (address 21h) 6.25.1 master volume control sets the volume of the signal out the dsp. 6.26 headphone volume control: hpa (address 22h) & hpb (address 23h) 6.26.1 headphone volume control sets the volume of the signal out the dac. treb[3:0] gain setting 0000 +12.0 db 0111 +1.5 db 1000 0 db 1001 -1.5 db 1111 -10.5 db step size: 1.5 db 76543210 mstxvol7 mstxvol6 mstxvol5 mstxvol4 mstxvol3 mstxvol2 mstxvol1 mstxvol0 mstxvol[7:0] master volume 0001 1000 +12.0 db 0000 0000 0 db 1111 1111 -0.5 db 1111 1110 -1.0 db 0011 0100 -102 db 0001 1001 -102 db step size: 0.5 db 76543210 hpxvol7 hpxvol6 hpxvol5 hpxvol4 hpxvol3 hpxvol2 hpxvol1 hpxvol0 hpxvol[7:0] headphone volume 0000 0000 0 db 1111 1111 -0.5 db 1111 1110 -1.0 db 0011 0100 -96.0 db 0000 0001 muted step size: 0.5 db
64 ds680a1 CS42L52 6.27 speaker volume control: spka (address 24h) & spkb (address 25h) 6.27.1 speaker volume control sets the volume of the signal out the pwm modulator. 6.28 adc & pcm channe l mixer (address 26h) 6.28.1 pcm mix channel swap configures a mix/swap of the pcm mix to the headphone/line or speaker outputs. 6.28.2 adc mix channel swap configures a mix/swap of the adc mix to the headphone/line or speaker outputs. 76543210 spkxvol7 spkxvol6 spkxvol5 spkxvol4 spkxvol3 spkxvol2 spkxvol1 spkxvol0 spkxvol[7:0] speaker volume 0000 0000 0 db 1111 1111 -0.5 db 1111 1110 -1.0 db 0100 0000 -96.0 db 0000 0001 muted step size: 0.5 db 76543210 pcmaswp1 pcmaswp0 pcmbswp1 pcmbswp0 adcaswp1 adcaswp0 adcbswp1 adcbswp0 pcmxswp[1:0] pcm mix to hp/lineouta pcm mix to hp/lineoutb 00 left right 01 (left + right)/2 (left + right)/2 10 11 right left adcxswp[1:0] adc mix to hp/lineouta channel adc mix to hp/lineoutb channel 00 left right 01 (left + right)/2 (left + right)/2 10 11 right left
ds680a1 65 CS42L52 6.29 limiter control 1, min/ max thresholds (address 27h) 6.29.1 limiter maximum threshold sets the maximum level, be low full scale, at which to limit and a ttenuate the output signal at the attack rate (limarate - ?limiter release rate? on page 66 ). note: bass, treble and digital gain settings that bo ost the signal beyond the maximum threshold may trigger an attack. 6.29.2 limiter cushion threshold sets the minimum level at which to disengage the limi ter?s attenuation at the release rate (limrrate - ?limiter release rate? on page 66 ) until levels lie between the lmax and cush thresholds. note: this setting is usually set sli ghtly below the lmax threshold. 6.29.3 limiter soft ramp disable configures an override of the digital soft ramp setting. note: this bit is ignored when the digzc ( ?digital zero cross? on page 53 ) is enabled. 76543210 lmax2 lmax1 lmax0 cush2 cush1 cush0 limsrdis limzcdis lmax[2:0] threshold setting 000 0 db 001 -3 db 010 -6 db 011 -9 db 100 -12 db 101 -18 db 110 -24 db 111 -30 db application: ?limiter? on page 31 cush[2:0] threshold setting 000 0 db 001 -3 db 010 -6 db 011 -9 db 100 -12 db 101 -18 db 110 -24 db 111 -30 db application: ?limiter? on page 31 limsrdis limiter soft ramp disable 0 off; limiter attack rate is dictated by the digsft ( ?digital soft ramp? on page 53 ) setting 1 on; limiter volume changes take effect in one step, regardless of the digsft setting. application: ?limiter? on page 31
66 ds680a1 CS42L52 6.29.4 limiter zero cross disable configures an override of the digital zero cross setting. 6.30 limiter control 2, release rate (address 28h) 6.30.1 peak detect and limiter configures the peak detect and limiter circuitry. 6.30.2 peak signal limit all channels sets how channels are attenuated when the limiter is enabled. 6.30.3 limiter release rate sets the rate at which the limiter releases the digita l attenuation from levels below the cush[2:0] thresh- old ( ?limiter cushion th reshold? on page 65 ) and returns the analog output level to the mstxvol[7:0] ( ?master volume control? on page 63 ) setting. note: the limiter release rate is user-selectable but is also a function of the sampling frequency, fs, and the digsft ( ?digital soft ramp? on page 53 ) and digzc ( ?digital zero cross? on page 53 ) setting. limzcdis limiter zero cross disable 0 off; limiter attack rate is dictated by the digzc ( ?digital zero cross? on page 53 ) setting 1 on; limiter volume changes take effect in one step, regardless of the digzc setting. application: ?limiter? on page 31 76543210 limit limit_all limrrate5 limrrate4 limrrate3 limrrate2 limrrate1 limrrate0 limit limiter status 0 disabled 1 enabled application: ?limiter? on page 31 limit_all limiter action: 0 apply the necessary attenuation on a specific channel only when the signal amplitude on that specific chan- nel rises above lmax. remove attenuation on a specific c hannel only when the signal amplitude on that specific channel falls below cush. 1 apply the necessary attenuation on both channels w hen the signal amplitude on any one channel rises above lmax. remove attenuation on both channels only when the signal amplitude on both channels fall below cush. application: ?limiter? on page 31 limrrate[5:0] release time 00 0000 fastest release 11 1111 slowest release application: ?limiter? on page 31
ds680a1 67 CS42L52 6.31 limiter attack rate (address 29h) 6.31.1 limiter attack rate sets the rate at which the limiter applies digital attenuation from le vels above the max[2:0] threshold ( ?limiter maximum threshold? on page 65 ). note: the limiter attack rate is user-selectable but is also a function of the sampling frequency, fs, and the digsft ( ?digital soft ramp? on page 53 ) and digzc ( ?digital zero cross? on page 53 ) setting unless the respective disable bit ( ?limiter soft ramp disable? on page 65 or ?limiter zero cross disable? on page 66 ) is enabled. 6.32 alc enable & atta ck rate (address 2ah) 6.32.1 alcx enable configures the automa tic level controller. 6.32.2 alc attack rate sets the rate at which the alc applies analog and/or digital attenuation from levels above the amax[2:0] threshold ( ?alc maximum threshold? on page 68 ). note: the alc attack rate is user-selectable but is al so a function of the sampling frequency, fs, and the anlgsftx ( ?ch. x analog soft ramp? on page 49 ) and anlgzcx ( ?ch. x analog zero cross? on page 49 ) setting unless the respective disable bit ( ?alcx soft ramp disable? on page 55 or ?alcx zero cross disable? on page 55 ) is enabled. 76543210 reserved reserved limarate5 limarate4 li marate3 limarate2 limarate1 limarate0 limarate[5:0] attack time 00 0000 fastest attack 11 1111 slowest attack application: ?limiter? on page 31 76543210 alcb alca alcarate5 aalcrate4 alcarate3 alcarate2 alcarate1 alcarate0 alc alc status 0 disabled 1 enabled application: ?automatic level control (alc)? on page 27 limarate[5:0] attack time 00 0000 fastest attack 11 1111 slowest attack application: ?automatic level control (alc)? on page 27
68 ds680a1 CS42L52 6.33 alc release rate (address 2bh) 6.33.1 alc release rate sets the rate at which the alc releases the analog and/or digital attenuation from levels below the min[2:0] threshold ( ?alc minimum threshold? on page 69 ) and returns the signal level to the pgax- vol[5:0] ( ?pgax volume? on page 56 ) and adcxvol[7:0] ( ?adcx volume? on page 57 ) setting. notes: 1. the alc release rate is user-selectable but is al so a function of the sampling frequency, fs, and the anlgsftx ( ?ch. x analog soft ramp? on page 49 ) and anlgzcx ( ?ch. x analog zero cross? on page 49 ) setting. 2. the release rate setting must alwa ys be slower than the attack rate. 6.34 alc threshold (address 2ch) 6.34.1 alc maximum threshold sets the maximum level, below full scal e, at which to limit and attenuate the input signal at the attack rate (alcarate - ?alc attack rate? on page 67 ). 76543210 reserved reserved alcrrate5 alcrrate4 alcrrate3 alcrrate2 alcrrate1 alcrrate0 alcrrate[5:0] release time 00 0000 fastest release 11 1111 slowest release application: ?automatic level control (alc)? on page 27 76543210 alcmax2 alcmax1 alcmax0 alcmin2 alcmin1 alcmin0 reserved reserved max[2:0] threshold setting 000 0 db 001 -3 db 010 -6 db 011 -9 db 100 -12 db 101 -18 db 110 -24 db 111 -30 db application: ?automatic level control (alc)? on page 27
ds680a1 69 CS42L52 6.34.2 alc minimum threshold sets the minimum level at which to disengage the alc?s attenuation or amplify the input signal at the re- lease rate (alcrrate - ?alc release rate? on page 68 ) until levels lie betwe en the alcmax and al- cmin thresholds. note: this setting is usually set sli ghtly below the alcmax threshold. 6.35 noise gate control (address 2dh) 6.35.1 noise gate all channels sets which channels are attenuated when clipping on any single channel occurs. 6.35.2 noise gate enable configures the noise gate. alcmin[2:0] threshold setting 000 0 db 001 -3 db 010 -6 db 011 -9 db 100 -12 db 101 -18 db 110 -24 db 111 -30 db application: ?automatic level control (alc)? on page 27 76543210 ngall ng ng_boost thresh2 thresh1 thresh0 ngdelay1 ngdelay0 ngall noise gate triggered by: 0 individual channel; any channel that falls below the threshold setting triggers the noise gate attenuation for both channels. 1 both channels a & b; both channels must fall below t he threshold setting for the noise gate attenuation to take effect. application: ?noise gate? on page 28 ng noise gate status 0 disabled 1 enabled application: ?noise gate? on page 28
70 ds680a1 CS42L52 6.35.3 noise gate threshold and boost thresh sets the threshold level of the noise gate. input signals below the thre shold level will be attenu- ated to -96 db. ng_boost configures a +30 db boost to the threshold settings. 6.35.4 noise gate delay timing sets the delay time before the noise gate attacks. note: the noise gate attack rate is a function of the sampling frequency, fs, and the anlgsftx ( ?ch. x analog soft ramp? on page 49 ) and anlgzcx ( ?ch. x analog zero cross? on page 49 ) setting unless the respective disable bit ( ?alcx soft ramp disable? on page 55 or ?alcx zero cross disable? on page 55 ) is enabled. 6.36 status (address 2eh) (read only) for all bits in this register, a ?1? means the associated error condition has occurred at least once since the register was last read. a?0? means the associated er ror condition has not occurred since the last reading of the register. reading the register resets all bits to 0. 6.36.1 serial port clock error (read only) indicates the status of the mclk to lrck ratio. note: on initial power up and application of clocks, this bit will report ?1?b as the serial port re-synchro- nizes. thresh[2:0] minimum setting (ng_boost = ?0?b) minimum setting (ng_boost = ?1?b) 000 -64 db -34 db 001 -67 db -37 db 010 -70 db -40 db 011 -73 db -43 db 100 -76 db -46 db 101 -82 db -52 db 110 reserved -58 db 111 reserved -64 db application: ?noise gate? on page 28 ngdelay[1:0] delay setting 00 50 ms 01 100 ms 10 150 ms 11 200 ms application: ?noise gate? on page 28 76543210 reserved spclkerr dspaovfl dspbovfl p cmaovfl pcmbovfl adcaovfl adcbovfl spclkerr serial port clock status: 0 mclk/lrck ratio is valid. 1 mclk/lrck ratio is not valid. application: ?serial port clocking? on page 34
ds680a1 71 CS42L52 6.36.2 dsp engine overflow (read only) indicates the over-range status in the dsp data path. 6.36.3 pcmx overflow (read only) indicates the over-range status in the pcm mix data path. 6.36.4 adcx overflow (read only) indicates the over-range status in the adc signal path. 6.37 battery compensation (address 2fh) 6.37.1 battery compensation configures automatic adjustment of the speaker volume when vp deviates from vpref[3:0]. 6.37.2 vp monitor configures the internal adc that monitors the vp voltage level. note: the internal adc that monitors the vp supply is enabled automatically when battcmp is en- abled, regardless of the vpmonitor setting. conv ersely, when battcmp is disabled, the adc may be enabled by enabling vpmonitor; this provides a convenient battery monitor without enabling battery compensation. dspxovfl dsp overflow status: 0 no digital clipping has occurred in the data path after the dsp. 1 digital clipping has occurred in the data path after the dsp. application: ?analog outputs? on page 29 pcmxovfl pcm overflow status: 0 no digital clipping has occurred in the data path of the pcm mix ( ?pcm mixer channel x volume? on page 58 ) of the dsp. 1 digital clipping has occurred in the data path of the pcm mix of the dsp. application: ?analog outputs? on page 29 adcxovfl adc overflow status: 0 no clipping has occurred anywhere in the adc signal path. 1 clipping has occurred in the adc signal path. application: ?analog inputs? on page 26 76543210 battcmp vpmonitor reserved reserved vpref3 vpref2 vpref1 vpref0 battcmp automatic battery compensation 0 disabled 1 enabled application: ?maintaining a desired output level? on page 34 vpmonitor vp adc status 0 disabled 1 enabled
72 ds680a1 CS42L52 6.37.3 vp reference sets the desired vp reference used for battery compensation. 6.38 vp battery level (add ress 30h) (read only) 6.38.1 vp voltage level (read only) indicates the unsigned vp voltage level. 6.39 speaker status (address 31h) (read only) 6.39.1 speaker current load status (read only) indicates whether or not any of the speaker outputs is shorted to ground. vpref[3:0] desired vp used to calculate the required attenuation on the speaker output: (for va = 1.8 v) 0000 1.5 v 0001 2.0 v 0010 2.5 v 0011 3.0 v 0100 3.5 v 0101 4.0 v 0110 4.5 v 0111 5.0 v (for va = 2.5 v) 1000 1.5 v 1001 2.0 v 1010 2.5 v 1011 3.0 v 1100 3.5 v 1101 4.0 v 1110 4.5 v 1111 5.0 v application: ?vp battery compensation? on page 33 76543210 vplvl7 vplvl6 vplvl5 vplvl4 vplvl3 vplvl2 vplvl1 vplvl0 vplvl[7:0] vp voltage ... 0101 1110 3.0 v (for va = 2.0 v); apply formula using actual va voltage to calculate vp voltage. ... 0111 0010 3.7 v (for va = 2.0 v); apply formula using actual va voltage to calculate vp voltage. ... formula: vp voltage = (binary representation of vplvl[7:0]) * va / 63.3 76543210 reserved reserved spkashrt spkbsh rt spkr/hp reserved twrn terr spkxshrt speaker output load 0 no overload detected 1 overload detected
ds680a1 73 CS42L52 6.39.2 spkr/hp pin status (read only) indicates the status of the spkr/hp pin. 6.39.3 thermal warning status (read only) indicates whether or not the codec?s die temper ature is approaching thermal error status. 6.39.4 thermal error status (read only) indicates whether or not the codec?s die tem perature has exceeded safe temperatures. 6.40 temperature monitor control (address 32h) 6.40.1 temperature acknowledge & release user-acknowledge input allowing the speaker output to resume normal operation after an automatic ther- mal-error-shutdown ( ?thermal error status (read only)? on page 73 ). note: when temperatures exceed the terrthr[2:0] and the speaker outputs power down, this bit must first be toggled from ?0?b to ?1?b and then back to ?0?b before the speaker powers up and resumes normal operation. 6.40.2 thermal foldback (address 33h) 6.40.3 thermal foldback configures automatic adjustment of the speaker volu me when the die temperature is approaching thermal error status. note: if thrfld is enabled and subsequently disabl ed when a thermal warning (indicated by twrn) is in progress, future automatic attenuation (specifi ed in spkattn) is disabled but the current automatic attenuation may remain for as long as ~512 ms befo re returning to th e volume specifie d in spkxvol[7:0]. spkr/hp pin state 0 pulled low 1 pulled high twrn thermal status 0 die temperature has not approached thermal error status. 1 die temperature is approaching thermal error status. terr thermal status 0 die temperature is within safe operating limits 1 die temperature has reached unsafe levels; speaker outputs will shut down immediately. 76543210 release reserved reserved reserved re served reserved reserved reserved release user action 0 remove automatic speaker-shutdown af ter thermal error is acknowledged 1 acknowledge thermal error 76543210 reserved reserved reserved reserv ed thrfld spkattn2 spkattn1 spkattn0 thrfld automatic speaker attenuation 0 disabled 1 enabled
74 ds680a1 CS42L52 6.40.4 speaker attenuation sets the speaker attenuation level when die temp erature is approaching thermal error status. note: the output levels of the affected channel re turns to the volume s pecified in spkxvol[7:0] ( ?speaker volume control? on page 64 ) after ~512 ms. 6.41 charge pump frequency (address 34h) 6.41.1 charge pump frequency sets the charge pump frequency on flyn and flyp. note: the headphone output thd+n pe rformance may be affected. spkattn[2:0] attenuation setting 000 0 db 001 1 db 010 2 db 011 3 db 100 4 db 101 5 db 110 6 db 111 7 db 76543210 chgfreq3 chgfreq2 chgfreq1 chgfreq0 r eserved reserved reserved reserved chgfreq[3:0] n 0000 0 ... 0101 5 ... 1111 15 formula: frequency = (64xfs)/(n+2)
ds680a1 75 CS42L52 7. analog performance plots 7.1 headphone thd+n versu s output power plots test conditions (unless otherwise specified): input test signal is a 997 hz sine wave; measurement band- width is 10 hz to 20 khz; fs = 48 khz. g = 0.6047 g = 0.7099 g = 0.8399 g = 1.0000 g = 1.1430 legend -100 -10 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 d b r a 0 80m 10m 20m 30m 40m 50m 60m 70m w figure 22. thd+n vs. output power per channel at 1.8 v (16 load) vhp = va = 1.8 v note: graph shows the out- put power per channel (i.e. output power = 23 mw into single 16 and 46 mw into stereo 16 with thd+n = - 75 db). g = 0.6047 g = 0.7099 g = 0.8399 g = 1.0000 g = 1.1430 legend -100 -10 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 d b r a 0 80m 10m 20m 30m 40m 50m 60m 70m w figure 23. thd+n vs. output power per channel at 2.5 v (16 load) vhp = va = 2.5 v note: graph shows the out- put power per channel (i.e. output power = 44 mw into single 16 and 88 mw into stereo 16 with thd+n = - 75 db).
76 ds680a1 CS42L52 g = 0.6047 g = 0.7099 g = 0.8399 g = 1.0000 g = 1.1430 legend -100 -20 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 d b r a 0 60m 6m 12m 18m 24m 30m 36m 42m 48m 54m w figure 24. thd+n vs. output power per channel at 1.8 v (32 load) vhp = va = 1.8 v note: graph shows the out- put power per channel (i.e. output power = 22 mw into single 32 and 44 mw into stereo 32 with thd+n = - 75 db). g = 0.6047 g = 0.7099 g = 0.8399 g = 1.0000 g = 1.1430 legend -100 -20 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 d b r a 0 60m 5m 10m 15m 20m 25m 30m 35m 40m 45m 50m 55m w figure 25. thd+n vs. output power per channel at 2.5 v (32 load) vhp = va = 2.5 v note: graph shows the out- put power per channel (i.e. output power = 42 mw into single 32 and 84 mw into stereo 32 with thd+n = - 75 db).
ds680a1 77 CS42L52 8. example system clock frequencies *the?mclkdiv2? bit must be enabled. 8.1 auto detect enabled 8.2 auto detect disabled sample rate lrck (khz) mclk (mhz) 1024x 1536x 2048x* 3072x* 8 8.1920 12.2880 16.3840 24.5760 11.025 11.2896 16.9344 22.5792 33.8688 12 12.2880 18.4320 24.5760 36.8640 sample rate lrck (khz) mclk (mhz) 512x 768x 1024x* 1536x* 16 8.1920 12.2880 16.3840 24.5760 22.05 11.2896 16.9344 22.5792 33.8688 24 12.2880 18.4320 24.5760 36.8640 sample rate lrck (khz) mclk (mhz) 256x 384x 512x* 768x* 32 8.1920 12.2880 16.3840 24.5760 44.1 11.2896 16.9344 22.5792 33.8688 48 12.2880 18.4320 24.5760 36.8640 sample rate lrck (khz) mclk (mhz) 128x 192x 256x* 384x* 64 8.1920 12.2880 16.3840 24.5760 88.2 11.2896 16.9344 22.5792 33.8688 96 12.2880 18.4320 24.5760 36.8640 sample rate lrck (khz) mclk (mhz) 512x 768x 1024x 1536x 2048x 3072x 8 - 6.1440 8.1920 12.2880 16.3840 24.5760 11.025 - 8.4672 11.2896 16.9344 22.5792 33.8688 12 6.1440 9.2160 12.2880 18.4320 24.5760 36.8640 sample rate lrck (khz) mclk (mhz) 256x 384x 512x 768x 1024x 1536x 16 - 6.1440 8.1920 12.2880 16.3840 24.5760 22.05 - 8.4672 11.2896 16.9344 22.5792 33.8688 24 6.1440 9.2160 12.2880 18.4320 24.5760 36.8640 sample rate lrck (khz) mclk (mhz) 256x 384x 512x 768x 32 8.1920 12.2880 16.3840 24.5760 44.1 11.2896 16.9344 22.5792 33.8688 48 12.2880 18.4320 24.5760 36.8640 sample rate lrck (khz) mclk (mhz) 128x 192x 256x 384x 64 8.1920 12.2880 16.3840 24.5760 88.2 11.2896 16.9344 22.5792 33.8688 96 12.2880 18.4320 24.5760 36.8640
78 ds680a1 CS42L52 9. pcb layout considerations 9.1 power supply, grounding as with any high-resolution converter, the CS42L52 requires careful attention to power supply and ground- ing arrangements if its potential performance is to be realized. figure 1 on page 10 shows the recommend- ed power arrangements, with va and vhp connected to clean supplies vd, which powers the digital circuitry, may be run from the system logic supply. al ternatively, vd may be powered from the analog supply via a ferrite bead. in this case, no additional devices should be powered from vd. extensive use of power and ground planes, ground plane fill in un used areas and surf ace mount decoupling capacitors are recommended. decoupling capacitors shou ld be as close to the pins of the CS42L52 as pos- sible. the low value ceramic capacitor should be cl osest to the pin and should be mounted on the same side of the board as the CS42L52 to minimize inductance effects. all signals, especially clocks, should be kept away fr om the filt+ and vq pins in order to avoid unwanted coupling into the modulators. the filt+ and vq decouplin g capacitors, particularly the 0.1 f, must be po- sitioned to minimize the electrical path from filt+ and agnd. the cdb42l52 evaluation board demon- strates the optimum layout and power supply arrangements. 9.2 qfn thermal pad the CS42L52 is available in a compact qfn package. the underside of the qfn package reveals a large metal pad that serves as a thermal relief to provide for maximum heat dissipation. this pad must mate with an equally dimensioned copper pad on the pcb and must be electrically connected to ground. a series of vias should be used to connect this copper pad to one or more larger ground planes on other pcb layers. in split ground systems, it is recommended that this thermal pad be connected to agnd for best perfor- mance. the CS42L52 evaluation board demonstrates the optimum thermal pad and via configuration.
ds680a1 79 CS42L52 10.adc & dac digital filters figure 26. adc passband ripple figure 27. adc stopband rejection figure 28. adc transition band figure 29. adc transition band detail figure 30. dac passband ripple figure 31. dac stopband figure 32. dac transition band figure 33. dac transition band (detail)
80 ds680a1 CS42L52 11.parameter definitions dynamic range the ratio of the rms value of the signal to the rms su m of all other spectral co mponents over the specified bandwidth. dynamic range is a signal-to-noise ratio measurement over the specif ied band width made with a -60 dbfs signal. 60 db is added to resulting measurement to refer the measurement to full-scale. this technique ensures that the distortion components are below the noise level and do not affect the measure- ment. this measurement te chnique has been accepted by the au dio engineering society, aes17-1991, and the electronic industries as sociation of japan, eiaj cp-307. expressed in decibels. total harmonic distortion + noise the ratio of the rms value of the signal to the rms su m of all other spectral co mponents over the specified band width (typically 10 hz to 20 khz), including di stortion components. expressed in decibels. measured at -1 and -20 dbfs as sug gested in aes17-1991 annex a. frequency response a measure of the amplitude response variation from 10 hz to 20 khz relative to the amplitude response at 1 khz. units in decibels. interchannel isolation a measure of crosstalk between the left and right chann el pairs. measured for each channel at the convert- er's output with no signal to the input under test and a full-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channel pairs. units in decibels. gain error the deviation from the nominal full-scale ana log output for a full-scale digital input. gain drift the change in gain value with temperature. units in ppm/c. offset error the deviation of the mid-scale transition (111... 111 to 000...000) from the ideal. units in mv.
ds680a1 81 CS42L52 12.package dimensions 1. dimensioning and tolerance per asme y 14.5m-1995. 2. dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm from the terminal tip. thermal characteristics inches millimeters note dim min nom max min nom max a -- -- 0.0394 -- -- 1.00 1 a1 0.0000 -- 0.0020 0.00 -- 0.05 1 b 0.0071 0.0091 0.0110 0.18 0.23 0.28 1 , 2 d 0.2362 bsc 6.00 bsc 1 d2 0.1594 0.1614 0.1634 4.05 4.10 4.15 1 e 0.2362 bsc 6.00 bsc 1 e2 0.1594 0.1614 0.1634 4.05 4.10 4.15 1 e 0.0197 bsc 0.50 bsc 1 l 0.0118 0.0157 0.0197 0.30 0.40 0.50 1 jedec #: mo-220 controlling dimension is millimeters. parameter symbol min typ max units junction to ambient thermal impedance 2 layer board 4 layer board ja - - 44 19 - - c/watt 40l qfn (6 x 6 mm body) package drawing e b a a1 pin #1 identifier ? 0.50 0.10 laser mar ki n g e 2.00 ref d2 l pin #1 corner 2.00 ref e2 d
82 ds680a1 CS42L52 13.ordering information 14.references 1. philips semiconductor, the i2c-bus specification: version 2.1 , january 2000. http://www.semiconductors.philips.com 15.revision history product description package pb-free grade temp range container order # CS42L52 low-power stereo codec w/hp and speaker amps for portable apps 40l-qfn yes commercial -40 to +85 c rail CS42L52-cnz tape & reel CS42L52-cnzr automotive -40 to +105 c rail CS42L52-dnz tape & reel CS42L52-dnzr cdb42l52 CS42L52 evaluation board - no - - - cdb42l52 crd42l52 CS42L52 reference design - no - - - crd42l52 revision changes a1 initial release contacting cirrus logic support for all product questions and inquiries, contact a cirrus logic sales representative. to find one nearest you, go to www.cirrus.com. important notice "advance" product information describes products that are in development and subject to development changes. cirrus logic, inc . and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant information t o verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limit ation of liability. no responsibility is assumed by cirrus fo r the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, co pyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information contained herein and gives conse nt for copies to be made of the infor- mation only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this conse nt does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semi conductor products may involve po tential risks of death, perso nal injury, or severe prop- erty or environmental damage (?critical applications?). cirr us products are not designed, au thorized or warranted for use in aircraft systems, military applications, products surgically implanted into the body, automotive safety or security de- vices, life support products or other critical applications. inclusion of cirrus products in such applications is under- stood to be fully at the customer?s ri sk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchan tability and fitness for par ticular purpose, with rega rd to any cirrus product that is used in such a manner. if the customer or customer?s cu stomer uses or permits the use of cirrus products in critical applications, customer agrees, by such u se, to fully indemnify cirrus, its officers , directors, employees, distributors and other agents from any and all liability, including attorneys? fe es and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. i2c is a registered trademark of philips semiconductor.

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